EDBA164B4PT-1DITF-R datasheet(28/152 Pages) MICRON

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Power-Up and Initialization

The device must be powered up and initialized in a predefined manner. Power-up and

initialization by means other than those specified will result in undefined operation.

Voltage Ramp and Device Initialization

The following sequence must be used to power up the device. Unless specified other-

wise, this procedure is mandatory (see the Voltage Ramp and Initialization Sequence

figure). Power-up and initialization by means other than those specified will result in

undefined operation.

1. Voltage Ramp Beginning

While applying power (after Ta), CKE must be held LOW (≤0.2 × VDD2), and all other in-

puts must be between VILmin and VIHmax. The device outputs remain at High-Z while

CKE is held LOW.

On or before the completion of the voltage ramp (Tb), CKE must be held LOW. DQ, DM,

DQS_t, and DQS_c voltage levels must be between VSSQ and VDDQ during voltage ramp

to avoid latchup. CK_t, CK_c, CS_n, and CA input levels must be between VSS and VDD2

during voltage ramp to avoid latchup.

The following conditions apply for voltage ramp:

• Ta is the point when any power supply first reaches 300mV.

• Noted conditions apply between Ta and power-down (controlled or uncontrolled).

• Tb is the point at which all supply and reference voltages are within their defined op-

erating ranges.

• Power ramp duration tINIT0 (Tb - Ta) must not exceed 20ms.

• For supply and reference voltage operating conditions, see the Recommended DC

Operating Conditions table.

• The voltage difference between any of VSS, and VSSQ pins must not exceed 100mV.

2. Voltage Ramp Completion

After Ta is reached:

•VDD1 must be greater than VDD2 - 200mV

•VDD1 and VDD2 must be greater than VDDQ - 200mV

•VREF must always be less than all other supply voltages

Beginning at Tb, CKE must remain LOW for at least tINIT1 = 100ns, after which CKE can

be asserted HIGH. The clock must be stable at least tINIT2 = 5 × tCK prior to the first

CKE LOW-to-HIGH transition (Tc). CKE, CS_n, and CA inputs must observe setup and

hold requirements (tIS, tIH) with respect to the first rising clock edge (and to subse-

quent falling and rising edges).

If any MRRs are issued, the clock period must be within the range defined for tCKb

(18ns to 100ns). MRWs can be issued at normal clock frequencies as long as all AC tim-

ings are met. Some AC parameters (for example, tDQSCK) could have relaxed timings

(such as tDQSCKb) before the system is appropriately configured. While keeping CKE

HIGH, NOP commands must be issued for at least tINIT3 = 200μs (Td).

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Power-Up and Initialization

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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