ES9026PRO datasheet(14/57 Pages) ESS

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CONFIDENTIAL ADVANCE INFORMATION v3.4

March 5, 2019

ES9026PRO 32-Bit HyperStream® II 8-Channel Audio DAC

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA. Tel (408) 643-

8800 • Fax (408) 643-8801

Serial Control Interface

The registers inside the chip are programmed via an I2C interface. The diagram below shows the timing for this interface.

Notes:

The CHIP ADDRESS is 0x92

The first byte after the CHIP ADDRESS (

“ADDRESS”) is the register address.

The second byte after the CHIP ADDRESS

(“DATA”) is the data to be programmed into the register

Multi-byte reads are NOT supported and will cause the I2C decoder to become unresponsive until a reset occurs.

I2C Timing Table

Start

Stop

Parameter

Symbol

MCLK

Constraint

Standard-Mode

Fast-Mode

Unit

MIN

MAX

MIN

MAX

SCL Clock Frequency

fSCL

< MCLK/20

100

400

kHz

START condition hold time

tHD,STA

4.0

0.6

s

LOW period of SCL

tLOW

>10/MCLK

4.7

1.3

s

HIGH period of SCL (>10/MCLK)

tHIGH

>10/MCLK

4.0

0.6

s

START condition setup time (repeat)

tSU,STA

4.7

0.6

s

SDA hold time from SCL falling

tHD,DAT

s

SDA setup time from SCL rising

tSU,DAT

250

100

Rise time of SDA and SCL

1000

300

Fall time of SDA and SCL

300

STOP condition setup time

tSU,STO

0.6

s

Bus free time between transmissions

tBUF

4.7

1.3

s

Capacitive load for each bus line

400

ADDR=1

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