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STM32G474CB 数据表(PDF) 21 Page - STMicroelectronics |
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STM32G474CB 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 236 page  DS12288 Rev 4 21/236 STM32G474xB STM32G474xC STM32G474xE Functional overview 48 3.6 Multi-AHB bus matrix The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs) and the slaves (Flash memory, RAM, FSMC, QUADSPI, AHB and APB peripherals). It also ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously. Figure 2. Multi-AHB bus matrix 3.7 Boot modes At startup, a BOOT0 pin (or nBOOT0 option bit) and an nBOOT1 option bit are used to select one of three boot options: • Boot from user Flash • Boot from system memory • Boot from embedded SRAM The BOOT0 value may come from the PB8-BOOT0 pin or from an nBOOT0 option bit depending on the value of a user nBOOT_SEL option bit to free the GPIO pad if needed. The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART, I2C, SPI, and USB through the DFU (device firmware upgrade). MSv42663V1 Cortex ®-M4 with FPU DMA1 DMA2 FSMC AHB2 peripherals AHB1 peripherals CCM SRAM SRAM1 FLASH 512 KB ICode DCode BusMatrix-S SRAM2 QUADSPI |
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