STSPIN32G4TR datasheet(32/48 Pages) STMICROELECTRONICS

32 / 48 page

Table 20. nFAULT output configuration register

Bit #

Bit name

Default

Description

NFAULT

Address 0x08

Protected

VDS_P_FLT

Signaling of the VDS protection triggering:

Enabled by default, 0 to disable

THSD _FLT

Signaling of the thermal shutdown status:

Enabled by default, 0 to disable

VCC_UVLO_FLT

Signaling of the VCC UVLO status:

Enabled by default, 0 to disable

Table 21. FAULT clear command register

Bit #

Bit name

Default

Description

CLEAR

Address 0x09

FAULT_CLEAR

Setting high all the bits clears all the latched failure

conditions.

Any other value is rejected.

Table 22. Standby register

Bit #

Bit name

Default

Description

STBY

Address 0x0A

Protected

STBY

Setting high the STBY bit requests the device to

enter low consumption mode.

Table 23. LOCK register

Bit #

Bit name

Default

Description

LOCK

Address 0x0B

NLOCK

When LOCK is different from the bitwise not of

NLOCK, the writing of the protected registers is

not allowed.

When LOCK is equal to the bitwise not of

NLOCK the writing of the protected registers is

allowed, and all gate driver outputs are forced

low.

LOCK

Table 24. RESET command register

Bit #

Bit name

Default

Description

RESET

Address 0x0C

Protected

RESET

Setting high all the bits resets the registers to the

default value.

Any other value is rejected.

STSPIN32G4

Control logic

DS13630 - Rev 1

page 32/48

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