ADIN1300CCPZ-R7 datasheet(6/79 Pages) AD

6 / 79 page

ADIN1300

Data Sheet

Rev. 0 | Page 6 of 79

TIMING CHARACTERISTICS

Power-Up Timing

Table 2. Power-Up Timing

Parameter

Description

Min

Typ

Max

Unit

tRAMP

Power supply ramp time

Minimum time interval to internal power good1

6.8

XTAL_I crystal settling time

1.5

XTAL_I external clock settling time

μs

Hardware configuration latch time

μs

Management interface active

The minimum time interval is referenced to the last supply to reach its rising threshold. There is no specific power supply sequencing required.

DVDD_0P9

XTAL_I

RESET_N

MDC

HARDWARE

CONFIGURATION

PINS

CONFIGURATION

LATCHED

DUAL FUNCTION

PINS ENABLED AS OUTPUTS

AVDD_3P3

FUNCTIONAL

STATE

POWER

GOOD

RESET RELEASED

CLOCKSTABILISING

HARDWARE

CONFIG LATCHED

MANAGEMENT

INTERFACE ACTIVE

VDDIO

SUPPLY

RAMP

POWER

OFF

tRAMP

Figure 2. Power-Up Timing

Hardware Reset Timing

Table 3. Hardware Reset Timing

Parameter

Description

Min

Typ

Max

Unit

RESET_N low time

μs

XTAL_I crystal settling time

1.5

XTAL_I external clock settling time

Hardware configuration latch time

μs

Management interface active

ADIN1300CCPZ-R7 数据表(PDF) 6 Page - Analog Devices

ADIN1300CCPZ-R7 数据表(HTML) 6 Page - Analog Devices

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