Application Notes

1. All of the controls on the evaluation board are brought out to a Molex test connector (J11) for

programmability. A 0V to +3.3V TTL signal can be used to override the dip switches (except for

the VADV, VADR, and VADJ switches). Set those dip switch positions to

OFF and apply a

+3.3V TTL signal (i.e., a logic “High” level) to the test header.

2. The evaluation board has an OP AMP to drive a Varactor VCO oscillator with a 0V to 20V tuning

voltage (see Figure 4). Make sure that the proper NO-LOAD resistors are installed to enable

the OP AMP circuitry (refer to the schematic in Figure 5) and make sure that a -5VEE and

+25VCC supply are connected. The -5V and +25V supplies are not needed if the OP AMP

integrator circuitry is not needed.

If evaluating the output charge pump circuit (i.e., UPN/UPP and DNP/DNN outputs), make sure

R12, R14, R24 and R26 (0 Ω) resistors are loaded. Also remove R17 and R21 (200 Ω)

resistors. If not, those two resistors (R17 and R21) will load down the phase detector charge

pump output circuit. However, it is ok to leave them in place during the evaluation if the output

level of the charge pump circuit is not a concern.

If using the Vtune (op-amp) output (J10) for evaluation, terminate the UPN/UPP and DNP/DNN

output ports with 50 Ω load to minimize reflection. This action will also lower the output

amplitude signal level by a small amount.

3. Figure 4 shows a block diagram of the PFD1K phase frequency detector and the VCO error

voltage integrator circuit (if loaded) that is part of the evaluation board.

4. A schematic of the evaluation board is included on the next page (figure 5).

Figure 4. Block diagram for PFD1KE evaluation PC board including loop filter and VCO op-amp

17 of 19

SMD-00191 Rev D

Subject to Change Without Notice

PFD1K