AS3933 datasheet(24/64 Pages) AMSCO

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[v1-08] 2015-Sep-02

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AS3933 − Detailed Description

Figure 24:

Default Values of Registers

Name

Type

Default

Value

Description

R0<7>

PAT32

R/W

Pattern extended to 32 bits (PAT32=0 16 bits, PAT32=1

32bits)

R0<6>

DAT_MAS

R/W

Masks data on DAT pin before wake-up (DAT_MASK = 0

→ data not masked; DAT_MASK = 1 → data masked)

R0<5>

ON_OFF

R/W

ON/OFF operation mode. (Duty-cycle defined in the

R0<4>

MUX_123

R/W

Scan mode enable

R0<3>

EN_A2

R/W

Channel 2 enable

R0<2>

EN_A3

R/W

Channel 3 enable

R0<1>

EN_A1

R/W

Channel 1 enable

R0<0>

Reserved

R1<7>

ABS_HY

R/W

Enable Data slicer absolute reference

R1<6>

AGC_TLIM

R/W

AGC acting only on the first carrier burst

R1<5>

AGC_UD

R/W

AGC operating in both direction (up-down)

R1<4>

ATT_ON

R/W

Antenna damper enable

R1<3>

EN_MANC

R/W

Manchester decoder enable

R1<2>

EN_PAT2

R/W

Double wake-up pattern correlation

R1<1>

EN_WPAT

R/W

Correlator enable

R1<0>

EN_XTAL

R/W

Crystal oscillator enable

R2<7>

S_ABSH

R/W

Data slicer absolute threshold reduction

R2<6>

EN_EXT_C

R/W

Enables external clock generator

R2<5>

G_BOOST

R/W

3dB Amplifier Gain Boost (G_BOOST=1)

R2<5>

Reserved

R2<3:2>

DISPLAY_

CLK

R/W

Set to 11 in case the clock generator's frequency is

shown on pin CL_DAT.

R2<1:0>

S_WU1

R/W

Tolerance setting for the stage wake-up (see Figure 37)

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