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DLPC4420ZPC 数据表(PDF) 21 Page - Texas Instruments

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部件名 DLPC4420ZPC
功能描述  DLPC4420 DLP짰 Display Controller
PDF  49 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DLPC4420ZPC 数据表(HTML) 21 Page - Texas Instruments

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6.11 DMD LVDS Interface Timing Requirements
FROM (INPUT)
TO (OUTPUT)
MIN
MAX
UNIT
fclock
Clock frequency, DCK_A
N/A
DCK_A
100
400
MHz
tC
Cycle time, DCK_A(1)
N/A
DCK_A
2475.3
ps
tW(H)
Pulse duration, high
N/A
DCK_A
1093
ps
tW(L)
Pulse duration, low
N/A
DCK_A
1093
ps
tt
Transition time, tt= tf/tr
N/A
DCK_A
100
400
ps
tosu
Output Setup time at max clock rate(2)
DCK_A↑↓
SCA, DDA(15:0)
438
ps
toh
Output hold time at max clock rate(2)
DCK_A↑↓
SCA, DDA(15:0)
438
ps
fclock
Clock frequency, DCK_B
N/A
DCK_B
100
400
MHz
tC
Cycle time, DCK_B(1)
N/A
DCK_B
2475.3
ps
tW(H)
Pulse duration, high
N/A
DCK_B
1093
ps
tW(L)
Pulse duration, low
N/A
DCK_B
1093
ps
tt
Transition time, tt= tf/tr
N/A
DCK_B
100
400
ps
tosu
Output Setup time at max clock rate(2)
DCK_B↑↓
SCA, DDB(15:0)
438
ps
toh
Output hold time at max clock rate(2)
DCK_B↑↓
SCA, DDB(15:0)
438
ps
tsk
Output Skew, Channel A to Channel B
DCK_A↑
DCK_B↑
250
ps
(1)
The minimum cycle time (tc) for DCK_A and DCL_B includes 1.0% spread spectrum modulation. User must verify that DMD can
support this rate.
(2)
Output Setup and Hold times for DMD clock frequencies below the maximum can be calculated as follows: tosu(fclock) = tosu(fmax) +
250000*(1/fclock – 1/400) and toh(fclock) = toh(fmax) + 250000*(1/fclock – 1/400) where fclock is in MHz.
6.12 Synchronous Serial Port (SSP) Interface Timing Requirements
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
SSP Primary
tsu
Setup time, SSPx_DI valid before SSPx_CLK
15
ns
tsu
Setup time, SSPx_DI valid before SSPx_CLK
15
ns
th
Hold time, SSPx_DI valid after SSPx_CLK
0
ns
th
Hold time, SSPx_DI valid after SSPx_CLK
0
ns
tt
Transition time, SSPx_DI, tt= tf/tr
20% to 80% reference points
(signal)
1.5
ns
SSP Secondary
tsu
Setup time, SSPx_DI valid before SSPx_CLK
12
ns
tsu
Setup time, SSPx_DI valid before SSPx_CLK
12
ns
th
Hold time, SSPx_DI valid after SSPx_CLK
12
ns
th
Hold time, SSPx_DI valid after SSPx_CLK
12
ns
tt
Transition time, SSPx_DI, tt= tf/tr
20% to 80% reference points
(signal)
1.5
ns
www.ti.com
DLPC4420
DLPS222 – DECEMBER 2021
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: DLPC4420



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