1 of 10

04-02-010F

s

s

s

s

High Speed/Low Power

- Speeds ranging from 7ns to 25ns

- Power as low as 30mA at 25MHz

s

s

s

s

Electrically Erasable Technology

- Superior factory testing

- Reprogrammable in plastic package

- Reduces retrofit and development costs

s

s

s

s

Development/Programmer Support

- Third party software and programmers

- Anachip PLACE Development Software

s

s

s

s

Architectural Flexibility

- 132 product term X 44 input AND array

- Up to 22 inputs and 10 outputs

- Up to 12 configurations per macrocell

- Synchronous preset, asynchronous clear

- Independent output enables

- 24-pin DIP/SOIC/TSSOP and 28-pin PLCC

s

s

s

s

Application Versatility

- Replaces random logic

- Pin and JEDEC compatible with 22V10

- Enhanced Architecture fits more logic

than ordinary PLDs

Features

The PEEL™22CV10A is a Programmable Electrically Eras-

able Logic (PEEL™) device providing an attractive alterna-

tive to ordinary PLDs. The PEEL™22CV10A offers the

performance, flexibility, ease of design and production

practicality

needed

by

logic

designers

today.

The

PEEL™22CV10A is available in 24-pin DIP, SOIC, TSSOP

and 28-pin PLCC packages (see Figure 1), with speeds

ranging from 7ns to 25ns and with power consumption as

low as 30mA. EE-reprogrammability provides the conve-

nience of instant reprogramming for development and a

reusable production inventory, minimizing the impact of

programming changes or errors. EE-reprogrammability

also improves factory testability, thus ensuring the highest

quality possible. The PEEL™22CV10A is JEDEC file com-

patible with standard 22V10 PLDs. Eight additional configu-

rations per macrocell (a total of 12) are also available by

using the “+” software/programming option (i.e., 22CV10A+

& 22CV10A++). The additional macrocell configurations

allow more logic to be put into every design. Programming

and development support for the PEEL™22CV10A are pro-

vided by popular third-party programmers and develop-

ment

software.

Anachip

also

offers

free

PLACE

development software.

General Description

DIP

*Optional extra ground pin for

-7/I-7 speed grade.

PLCC

1

2

3

4

5

6

7

8

I/CLK

I

I

I

I

I

I

I

VCC

I/O

I/O

I/O

I/O

I/O

I/O

I/O

24

23

22

21

20

19

18

17

9

10

I

I

I/O

I/O

16

15

11

12

I

GND

I/O

I

14

13

TSSOP

SOIC

Figure 1. Pin Configuration

Figure 2. Block Diagram

CMOS Programmable Electrically Erasable Logic Device

PEEL™ 22CV10A -7/-10/-15/-25