AD9540BCPZ datasheet(19/32 Pages) AD

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AD9540

Rev. 0 | Page 19 of 32

GENERAL DESCRIPTION

PLL CIRCUITRY

The AD9540 includes an RF divider (divide-by-R), a 48-bit DDS

core, a 14-bit programmable delay adjustment, a 10-bit DAC, a

phase frequency detector, and a programmable output current

charge pump. Incorporating these blocks together, users can

generate many useful circuits for clock synthesis. A few simple

examples are shown in the Typical Performance Characteristics

section.

The RF divider accepts differential or single-ended signals up to

2.7 GHz on the CLK1 input pin. The RF divider also supplies

the SYSCLK input to the DDS. Because the DDS operates only

up to 400 MSPS, device function requires that for any CLK1

signal > 400 MHz, the RF divider must be engaged. The RF di-

vider can be programmed to take values of 1, 2, 4, or 8. The ratio

for the divider is programmed in the control register. The out-

put of the divider can be routed to the input of the on-chip

CML driver. For lower frequency input signals, it is possible to

use the divider to divide the input signal to the CML driver and

to use the undivided input of the divider as the SYSCLK input

to the DDS, or vice versa. In all cases, the clock to the DDS

should not exceed 400 MSPS.

The on-chip phase frequency detector has two differential

inputs, REFIN (the reference input) and CLK2 (the feedback or

oscillator input). These differential inputs can be driven by

single-ended signals. When doing so, tie the unused input

through a 100 pF capacitor to the analog supply (AVDD). The

maximum speed of the phase frequency detector inputs is

200 MHz. Each of the inputs has a buffer and a divider (÷M on

REFIN and ÷N on CLK2) that operates up to 655 MHz. If the

signal exceeds 200 MHz, the divider must be used. The dividers

are programmed through the control registers and take any

integer value between 1 and 16.

The REFIN input also has the option of engaging an in-line

oscillator circuit. Engaging this circuit means that the REFIN

input can be driven with a crystal in the range of 20 MHz ≤

REFIN ≤ 30 MHz.

The charge pump outputs a current in response to an error

signal generated in the phase frequency detector. The output

current is programmed through by placing a resistor (CP_RSET)

from the CP_RSET pin to ground. The value is dictated by:

SET

CP_R

CP_IOUT

1.55

This sets the charge pump’s reference output current. Also, a

programmable scaler multiplies this base value by any integer

from 1 to 8, programmable through the CP current scale bits in

the Control Function Register 2, CFR2<2:0>.

CML DRIVER

An on-chip current mode logic (CML) driver is also included.

This CML driver generates very low jitter clock edges. The

outputs of the CML driver are current outputs that drive PECL

levels when terminated into a 100 Ω load. The continuous

output current of the driver is programmed by attaching a resis-

tor from the DRV_RSET pin to ground (nominally 4.02 kΩ for

a continuous current of 7.2 mA). An optional on-chip current

programming resistor is enabled by setting a bit in the control

pendently programmable to help control overshoot and ringing

by the application of surge current during rising edge and

falling edge transitions (see Figure 34). There is a default surge

current of 7.6 mA on the rising edge and of 4.05 mA on the

falling edge. Bits in the control register enable additional rising

edge and falling edge surge current, as well disable the default

surge current (see the Control Function Register Descriptions

section for details). The CML driver can be driven by:

•

RF divider input (CLK1 directly to the CML driver)

•

RF divider output

•

CLK2 input

I(t)

~250ps

RISING EDGE SURGE

CONTINUOUS

FALLING EDGE SURGE

Figure 34. Rising Edge and Falling Edge Surge Current Out of the

CML Clock Driver, as Opposed to the Steady State Continuous Current

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