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USB7252 数据表(PDF) 52 Page - Microchip Technology |
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USB7252 数据表(HTML) 52 Page - Microchip Technology |
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52 / 65 page ![]() USB7252 DS00002736D-page 52 2018 - 2020 Microchip Technology Inc. 9.6.10 SPI/SQI MASTER TIMING This section specifies the SPI/SQI master timing requirements for the device. FIGURE 9-7: SPI/SQI MASTER TIMING TABLE 9-9: SPI/SQI MASTER TIMING (30 MHZ OPERATION) Symbol Description Min Typ Max Units tfc Clock frequency 30 MHz tceh Chip enable ( SPI_CE_N) high time 100 ns tclq Clock to input data 13 ns tdh Input data hold time 0 ns tos Output setup time 5 ns toh Output hold time 5 ns tov Clock to output valid 4 ns tcel Chip enable ( SPI_CE_N) low to first clock 12 ns tceh Last clock to chip enable ( SPI_CE_N) high 12 ns TABLE 9-10: SPI/SQI MASTER TIMING (60 MHZ OPERATION) Symbol Description Min Typ Max Units tfc Clock frequency 60 MHz tceh Chip enable ( SPI_CE_N) high time 50 ns tclq Clock to input data 9 ns tdh Input data hold time 0 ns tos Output setup time 5 ns toh Output hold time 5 ns tov Clock to output valid 4 ns tcel Chip enable ( SPI_CE_N) low to first clock 12 ns tceh Last clock to chip enable ( SPI_CE_N) high 12 ns SPI_CLK SPI_D[3:0] (in) SPI_D[3:0] (out) SPI_CE_N tcel tfc Output data valid tclq tceh tdh toh tos tov toh Output data valid Input data valid tceh |
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