1

PS8744A

06/23/05

Features

• Four Pairs of Differential Clocks

• Low skew < 50ps

• Low jitter < 50ps

• Output Enable for all outputs

• Outputs tristate control via SMBus

• Power Management Control

• Programmable PLL Bandwidth

• PLL or Fanout operation

• 3.3V Operation

• Packaging:

- 28-Pin SSOP (H) & 28-Pin TSSOP (L)

- Pb-Free and Green Option (HE and LE)

PI6C20400

Description

Pericom Semiconductors PI6C20400 is a high-speed, low-noise

differential clock buffer designed to be companion to PI6C410B.

The device distributes the differential SRC clock from PI6C410B

to four differential pairs of clock outputs either with or without

PLL. The clock outputs are controlled by input selection of

SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When

input of either SRC_STOP# or PWRDWN# is low, the output

clocks are Tristated. When PWRDWN# is low, the SDA and

SCLK inputs must be Tristated.

Block Diagram

1:4 Clock Driver for Intel

PCI Express Chipsets

Pin Configuration

OE_INV

OUT3

OUT3#

OE_3

OUT2

OUT2#

PLL_BW#

SRC_STOP#

PWRDWN#

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

SRC

SCR#

OUT0

OUT0#

OE_0

OUT1

OUT1#

PLL/BYPASS#

SCLK

SDA

OUT0

OUT0#

OUT0

OUT1#

OUT2

OUT2#

OUT3

OUT3#

DIV

Output

Control

SMBus

Controller

PLL

PLL_BW#

SRC

SRC#

PLL/BYPASS#

SCLK

SDA

OE_INV

OE_0 & OE_3

SRC_STOP#

PWRDWN#