ADP7112ACBZ-1.2-R7 datasheet(20/21 Pages) AD

20 / 21 page

ADP7112

Data Sheet

Rev. D | Page 20 of 21

Table 7. Recommended LDOs for Super Low Noise Operation

Device

Number

VIN

Range (V)

VOUT

Fixed (V)

VOUT Adjust

(V)

IOUT

(mA)

IQ at

IOUT

(μA)

IGND-SD

Max

(μA)

Soft

Start

PGOOD

Noise

(Fixed)

10 Hz to

100 kHz

(μV rms)

PSRR

100 kHz

(dB)

PSRR

1 MHz

(dB)

Package

ADP7102

3.3 to 20

1.5 to 9

1.22 to 19

300

750

Yes

3 mm ×

3 mm

8-lead LFCSP,

8-lead SOIC

ADP7104

3.3 to 20

1.5 to 9

1.22 to 19

500

900

Yes

3 mm ×

3 mm

8-lead LFCSP,

8-lead SOIC

ADP7105

3.3 to 20

1.8, 3.3, 5

1.22 to 19

500

900

Yes

3 mm ×

3 mm

8-lead LFCSP,

8-lead SOIC

ADP7112

2.7 to 20

1.2 to 5

1.2 to 19

200

180

Yes

1 mm ×

1.2 mm

6-ball WLCSP

ADP7118

2.7 to 20

1.2 to 5

1.2 to 19

200

180

Yes

2 mm ×

2 mm

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

ADP7142

2.7 to 40

1.2 to 5

1.2 to 39

200

180

Yes

2 mm ×

2 mm

6-lead LFCSP,

8-lead SOIC,

5-lead TSOT

ADP7182

−2.7 to −28

−1.8 to −5

−1.22 to −27

−200

−650

−8

2 mm ×

2 mm

6-lead LFCSP,

3 × 3 mm

8-lead LFCSP,

5-lead TSOT

Table 8. Related Devices

Model

Input Voltage (V)

Output Current (mA)

Package

ADP7118ACP

2.7 to 20

200

6-lead LFCSP

ADP7118ARD

2.7 to 20

200

8-lead SOIC

ADP7118AUJ

2.7 to 20

200

5-lead TSOT

ADP7142ACP

2.7 to 40

200

6-lead LFCSP

ADP7142ARD

2.7 to 40

200

8-lead SOIC

ADP7142AUJ

2.7 to 40

200

5-lead TSOT

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