ADP7185ACPZN3.3-R7 datasheet(13/19 Pages) AD

13 / 19 page

Data Sheet

ADP7185

Rev. 0 | Page 13 of 19

THEORY OF OPERATION

The ADP7185 is a low quiescent current, LDO linear regulator

that operates from −2.0 V to −5.5 V and can provide up to

−500 mA of output current. Total integrated output noise is

4 μV rms independent of the output voltage, making it ideal for

high performance and noise sensitive applications. Shutdown

current consumption is −7 μA (maximum).

The ADP7185 is optimized for use with a 4.7 μF ceramic

capacitor for excellent transient performance. Using advanced

proprietary architecture, the ADP7185 provides ultralow noise

and high power supply rejection up to high frequencies of

operation. Figure 40 shows the fixed output voltage internal block

diagram of the ADP7185, and Figure 41 shows the adjustable

output voltage internal block diagram of the ADP7185.

VAFB

OVER CURRENT

THERMAL

PROTECTION

REFERENCE

–0.5V

REG

GND

VREG

VIN

SENSE

VOUT

Figure 40. Fixed Output Voltage Internal Block Diagram

OVER CURRENT

THERMAL

PROTECTION

REFERENCE

–0.5V

REG

GND

VREG

VIN

VAFB

SENSE

VOUT

Figure 41. Adjustable Output Voltage Internal Block Diagram

Internally, the ADP7185 consists of a regulator block, reference

block, GM amplifier, feedback voltage divider, LDO regulator, and an

N-channel MOSFET pass transistor. The regulator block produces

an internal voltage rail (VREG) of −1.8 V to serve as the supply

voltage for the succeeding internal blocks. The GM amplifier

produces a reference voltage (VA) used as a reference to the

LDO regulator.

For fixed option models, the VA voltage is generated through the

resistor divider ratio depending on the VOUT option. For adjustable

models, the VA voltage generates externally through the R1 and

R2 resistors that are connected across the VA and VAFB pins.

Because the reference voltage to the LDO regulator already

adjusts according to the desired VOUT, the LDO regulator now

connects in a buffer configuration for improved noise performance.

If the load draws higher current, the LDO regulator pulls the gate

of the NMOS device higher towards GND to allow more current

to pass. If the load draws less current, the LDO regulator pulls

the gate of the NMOS device lower toward −VIN to restrict the

amount of current passing through the device.

ADJUSTABLE MODE OPERATION

The adjustable mode version of the ADP7185 has an output that

can be set to from −0.5 V to −4.5 V by an external voltage divider.

To calculate the output voltage, use the following equation:

VOUT = −0.5 V(1 + R1/R2)

(1)

Figure 42 shows an example of an adjustable setting where R1 =

280 kΩ and R2 = 49.9 kΩ, setting the output voltage to −3.3 V.

R2 must be at least 10 kΩ to maximize PSRR performance.

CIN

4.7µF

VIN = –3.8V

+1.25V

–1.3V

OFF

VOUT = –3.3V

CREG

1µF

VIN

VREG

GND

VOUT

SENSE

VAFB

ADP7185

COUT

4.7µF

1µF

280kΩ

49.9kΩ

CAFB

10nF

Figure 42. Setting the Adjustable Output Voltage

ENABLE PIN OPERATION

The ADP7185 uses the EN pin to enable and disable the VOUT pin

under normal operating conditions. When EN is +1.25 V above or

−1.3 V below with respect to GND, VOUT turns on, and when

EN is at 0 V, VOUT turns off, as shown in Figure 43. For

automatic startup, connect EN to VIN.

CH1 1.0V

–15mV

CH2 1.0V

0mV

200ms/DIV

2MS 1MS/s

A CH2

40mV

VOUT

Figure 43. Typical EN Pin Operation

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