Data Sheet

ADP1764

Rev. A | Page 15 of 20

APPLICATIONS INFORMATION

CAPACITOR SELECTION

Output Capacitor

The ADP1764 is designed for operation with small, space-saving

ceramic capacitors, but it can function with most commonly used

capacitors as long as care is taken with the effective series

resistance (ESR) value. The ESR of the output capacitor affects

the stability of the LDO control loop. A minimum of 22 μF

capacitance with an ESR of 50 mΩ or less is recommended to

ensure the stability of the ADP1764. Transient response to changes

in load current is also affected by output capacitance. Using a larger

value of output capacitance improves the transient response of the

ADP1764 to large changes in load current. Figure 46 and Figure 47

show the transient responses for output capacitance values of 22 μF

and 47 μF, respectively.

CH1 50mV

CH3 2A

4.00µs

5GSPS

1M POINTS

CH3

2.44A

T

11.04000µs

3

1

T

SLEW RATE = 5A/µs

B

W

B

W

CH1 50mV

CH3 2A

4.00µs

5GSPS

1M POINTS

CH3

2.44A

T

11.16000µs

3

1

T

SLEW RATE = 5A/µs

B

W

B

W

Input Bypass Capacitor

Connecting a 22 μF capacitor from the VIN pin to the GND pin

to the ground plane reduces the circuit sensitivity to the PCB

layout, especially when long input traces or high source imped-

ances are encountered. If an output capacitance greater than 22 μF

is required, it is recommended to increase the input capacitor to

match it.

Input and Output Capacitor Properties

Use any good quality ceramic capacitors with the ADP1764 as

long as they meet the minimum capacitance and maximum ESR

requirements. Ceramic capacitors are manufactured with a variety

of dielectrics, each with different behavior over temperature and

applied voltage. Capacitors must have a dielectric adequate to

ensure the minimum capacitance over the necessary temperature

range and dc bias conditions. X5R or X7R dielectrics with a voltage

rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics

are not recommended, due to their poor temperature and dc bias

characteristics.

Figure 48 shows the capacitance vs. dc bias voltage characteristics

of a C2012X5R1A226K125AB, 0805 case, 22 μF, 10 V, X5R

capacitor. The voltage stability of a capacitor is strongly influenced

by the capacitor size and voltage rating. In general, a capacitor

in a larger package or with a higher voltage rating exhibits

improved stability. The temperature variation of the X5R

dielectric is about ±15% over the −55°C to +85°C temperature

range and is not a function of package size or voltage rating.

25

0

5

10

15

20

02

4

68

10

DC BIAS VOLTAGE (V)

Figure 48. Capacitance vs. DC Bias Voltage

Use Equation 4 to determine the worst-case capacitance,

accounting for capacitor variation over temperature, component

tolerance, and voltage.

(4)

where:

TEMPCO is the worst case capacitor temperature coefficient.

TOL is the worst case component tolerance.

In this example, the worst case temperature coefficient

(TEMPCO) over −55°C to +125°C is assumed to be 15% for an

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

Substituting these values in Equation 4 yields