STM32MP153D datasheet(42/256 Pages) STMICROELECTRONICS

42 / 256 page

Functional overview

STM32MP153A/D

42/256

DS12502 Rev 6

The accelerator supports DMA request generation.

HASH1 can be defined (in ETZPC) as accessible by secure software only.

3.32

Boot and security and OTP control (BSEC)

The BSEC (boot and security and OTP control) is intended to control an OTP (one time

programmable) fuse box, used for embedded non-volatile storage for device configuration

and security parameters. Some part of BSEC should be configured as accessible by secure

software only.

3.33

Timers and watchdogs

The devices include two advanced-control timers, ten general-purpose timers, two basic

timers, five low-power timers, three watchdogs, a SysTick timer in Cortex-M4 and 4 system

timers in each Cortex-A7.

All timer counters can be frozen in debug mode.

Table 4 compares the features of the advanced-control, general-purpose, basic and low-

power timers.

Table 4. Timer feature comparison

Timer

type

Timer

Counter

resolution

Counter

type

Prescaler

factor

DMA

request

generation

Capture/

compare

channels

Comple-

mentary

output

Max

interface

clock

(MHz)

Max

timer

clock

(MHz)(1)

Advanced

-control

TIM1,

TIM8

16-bit

Up,

down,

up/down

Any integer

between 1

and 65536

Yes

104.5

209

General

purpose

TIM2,

TIM5

32-bit

Up,

down,

up/down

Any integer

between 1

and 65536

Yes

104.5

209

TIM3,

TIM4

16-bit

Up,

down,

up/down

Any integer

between 1

and 65536

Yes

104.5

209

TIM12

16-bit

Any integer

between 1

and 65536

104.5

209

TIM13,

TIM14

16-bit

Any integer

between 1

and 65536

104.5

209

TIM15

16-bit

Any integer

between 1

and 65536

Yes

104.5

209

TIM16,

TIM17

16-bit

Any integer

between 1

and 65536

Yes

104.5

209

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