Data Sheet

ADP165/ADP166

THEORY OF OPERATION

The ADP165/ADP166 are very low quiescent current, low dropout

linear regulators that operate from 2.2 V to 5.5 V and can provide

up to 150 mA of output current. Drawing only 590 nA (typical)

at no load and a low 42 µA of quiescent current (typical) at full load

makes the ADP165/ADP166 ideal for battery-operated portable

equipment. Shutdown current consumption is typically 50 nA.

Using new innovative design techniques, the ADP165/ADP166

provide very low quiescent current and superior transient

performance for digital and RF applications. The ADP165/

ADP166 are also optimized for use with small 1 µF ceramic

capacitors.

REFERENCE

CURRENT-LIMIT,

UVLO, AND

THERMAL

PROTECTION

SHUTDOWN

R1

R2

VOUT

VIN

GND

EN

ADP165

R3

Figure 32. Internal Block Diagram, Fixed Output with Output Discharge

Function

REFERENCE

CURRENT-LIMIT,

UVLO, AND

THERMAL

PROTECTION

SHUTDOWN

VOUT

ADJ

VIN

GND

EN

ADP165

R1

Figure 33. Internal Block Diagram, Adjustable Output with Output Discharge

Function

REFERENCE

CURRENT-LIMIT,

UVLO, AND

THERMAL

PROTECTION

SHUTDOWN

R1

R2

VOUT

VIN

GND

EN

ADP166

Figure 34. Internal Block Diagram, Fixed Output Without Output Discharge

Function

REFERENCE

CURRENT-LIMIT,

UVLO, AND

THERMAL

PROTECTION

SHUTDOWN

VOUT

ADJ

VIN

GND

EN

ADP166

Figure 35. Internal Block Diagram, Adjustable Output Without Output

Discharge Function

Internally, the ADP165/ADP166 consist of a reference, an error

amplifier, a feedback voltage divider, and a PMOS pass transistor.

Output current is delivered via the PMOS pass device, which is

controlled by the error amplifier. The error amplifier compares the

reference voltage with the feedback voltage from the output and

amplifies the difference. If the feedback voltage is lower than the

reference voltage, the gate of the PMOS device is pulled lower,

allowing more current to pass and increasing the output voltage.

If the feedback voltage is higher than the reference voltage, the

gate of the PMOS device is pulled higher, allowing less current to

pass and decreasing the output voltage.

The adjustable ADP165/ADP166 have an output voltage range

of 1.0 V to 4.2 V. The output voltage is set by the ratio of two

external resistors, which are the same as the R1 and R2 resistors in

Figure 32 and Figure 34, but are connected through the ADJ pin.

The device servos the output to maintain the voltage at the ADJ pin

at 1.0 V referenced to ground. The current in R1 is then equal

to 1.0 V/R2, and the current in R1 is the current in R2 plus the

ADJ pin bias current. The ADJ pin bias current, 10 nA at 25°C,

flows through R1 into the ADJ pin.

Calculate the output voltage using the following equation:

The value of R1 must be less than 200 kΩ to minimize errors in the

output voltage caused by the ADJ pin bias current. For example,

when R1 and R2 each equal 200 kΩ, the output voltage is 2.0 V.

The output voltage error introduced by the ADJ pin bias current

is 2 mV or 0.05%, assuming a typical ADJ pin bias current of

10 nA at 25°C.

Rev. A | Page 13 of 23