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L99UDL01 数据表(PDF) 16 Page - STMicroelectronics |
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L99UDL01 数据表(HTML) 16 Page - STMicroelectronics |
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16 / 24 page ![]() Device description L99UDL01 16/24 DB3264 Rev 3 Figure 6. State diagram In Sleep mode no active circuitry is supplied. In standby mode logic is initialized but not operational. There is no function present in either modes in order to minimize the current consumption. Only wake-up circuitry is active in Standby mode. 2.5.1 Sleep mode In sleep mode all circuitry is disabled. There is no charge pump or internal voltages. This is the lowest quiescent current mode. Sleep mode is entered when the VDD input falls below VDDSLEEP. Prior to entering sleep mode all registers are reset to their default values. Sleep mode is exited when VDD rises above VDDSLEEP. Sleep mode only exits into Standby mode. 2.5.2 Standby mode Standby mode has only the 3V3 pre-regulator active for purposes of watching for wake-up. The charge pump is off and the outputs are disabled. Standby is entered, from operational mode, when the device is commanded by SPI message (it requires two bits set in two different registers) or by VDD falling below VDDUV. To attain the low quiescent state in Standby the EN_OUT pin must be held low. Standby cannot be entered while in timed actuation or when any output is active. This operation is not supported. |
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