STM32L031C4 datasheet(21/126 Pages) STMICROELECTRONICS

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DS10668 Rev 6

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STM32L031x4/6

Functional overview

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L031x4/6 embed a nested vectored interrupt controller able to

handle up to 32 maskable interrupt channels and 4 priority levels.

The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt

Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:

•

includes a Non-Maskable Interrupt (NMI)

•

provides zero jitter interrupt option

•

provides four interrupt priority levels

The tight integration of the processor core and NVIC provides fast execution of Interrupt

Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved

through the hardware stacking of registers, and the ability to abandon and restart load-

multiple and store-multiple operations. Interrupt handlers do not require any assembler

wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also

significantly reduces the overhead when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a

deep sleep function that enables the entire device to enter rapidly stop or standby mode.

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

3.4

Reset and supply management

3.4.1

Power supply schemes

•

VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided

externally through VDD pins.

•

VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs

and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.

3.4.2

Power supply supervisor

The devices feature an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR) that can be coupled with a brownout reset (BOR) circuitry.

Two versions are available:

•

The version with BOR activated at power-on operates between 1.8 V and 3.6 V.

•

The other version without BOR operates between 1.65 V and 3.6 V.

After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or

not at power-on), the option byte loading process starts, either to confirm or modify default

thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes

1.65 V (whatever the version, BOR active or not, at power-on).

When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever

the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the

power ramp-up must guarantee that 1.65 V is reached on VDD at least 1 ms after it exits the

POR area.

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To

reduce the power consumption in Stop mode, it is possible to automatically switch off the

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