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M68AW256DL

OPERATION

The M68AW256DL has a Chip Enable power

down feature which invokes an automatic standby

mode whenever Chip Enable is de-asserted (E1 =

High) or Chip Select is asserted (E2 = Low), or UB/

LB are de-asserted (UB/LB = High). An Output En-

able (G) signal provides a high speed tri-state con-

trol, allowing fast read/write cycles to be achieved

with the common I/O data bus. Operational modes

are determined by device control inputs W, E1, LB

and UB as summarized in the Operating Modes ta-

ble (see Table 6).

Table 6. Operating Modes

Read Mode

The M68AW256DL, when Chip Select (E2) is

High, is in the read mode whenever Write Enable

(W) is High with Output Enable (G) Low, and Chip

Enable (E1) is asserted. This provides access to

data from eight or sixteen, depending on the status

of the signal UB and LB, of the 4,194,304 locations

in the static memory array, specified by the 18 ad-

dress inputs. Valid data will be available at the

last stable address, providing G is Low and E1 is

Low. If Chip Enable or Output Enable access

times are not met, data access will be measured

rather than the address. Data out may be indeter-

Figure 8. Address Controlled, Read Mode AC Waveforms

Note: E1 = Low, E2 = High, G = Low, W = High, UB = Low and/or LB = Low.

Operation

E1

E2

W

G

LB

UB

DQ0-DQ7

DQ8-DQ15

Power

Deselected

X

X

X

X

X

Hi-Z

Hi-Z

Deselected

X

X

X

X

X

Hi-Z

Hi-Z

Deselected

X

X

X

X

Hi-Z

Hi-Z

Lower Byte Read

Data Output

Hi-Z

Lower Byte Write

X

Data Input

Hi-Z

Output Disabled

X

X

Hi-Z

Hi-Z

Upper Byte Read

Hi-Z

Data Output

Upper Byte Write

X

Hi-Z

Data Input

Word Read

Data Output

Data Output

Word Write

X

Data Input

Data Input

AI03956

tAVAV

tAVQV

tAXQX

A0-A17

DQ0-DQ7 and/or DQ8-DQ15

VALID

DATA VALID