AD7475ARMZ datasheet(13/24 Pages) AD

13 / 24 page

Data Sheet

AD7475/AD7495

Rev. D | Page 13 of 24

THEORY OF OPERATION

The AD7475/AD7495 are fast, micropower, 12-bit, single-

supply analog-to-digital converters (ADCs). The devices can be

operated from a 2.7 V to 5.25 V supply. When operated from

either a 5 V supply or a 3 V supply, the AD7475/AD7495 are

capable of throughput rates of 1 MSPS when provided with a

20 MHz clock.

The AD7475/AD7495 ADCs have an on-chip track-and-hold

with a serial interface housed in either an 8-lead SOIC or MSOP

package, features that offer the user considerable space-saving

advantages over alternative solutions. The AD7495 also has an

on-chip 2.5 V reference. The serial clock input accesses data from

the device but also provides the clock source for the successive-

approximation ADC. The analog input range is 0 V to REF IN

for the AD7475 and 0 V to REF OUT for the AD7495.

The AD7475/AD7495 also feature power-down options to allow

power saving between conversions. The power-down feature is

implemented across the standard serial interface, as described

in the Operating Modes section.

CONVERTER OPERATION

The AD7475/AD7495 are 12-bit, successive approximation

analog-to-digital converters based around a capacitive DAC.

The AD7475/AD7495 can convert analog input signals in the

range 0 V to 2.5 V. Figure 10 and Figure 12 show simplified

schematics of the ADC. The ADC comprises control logic, SAR,

and a capacitive DAC, which are used to add and subtract fixed

amounts of charge from the sampling capacitor to bring the

comparator back into a balanced condition. Figure 10 shows the

ADC during its acquisition phase. SW2 is closed and SW1 is in

Position A. The comparator is held in a balanced condition and

the sampling capacitor acquires the signal on VIN.

COMPARATOR

VIN

CONTROL LOGIC

CAPACITIVE

DAC

AGND

Ω

SW2

SW1

Figure 10. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 11), SW2 opens

and SW1 moves to Position B causing the comparator to become

unbalanced. The control logic and the capacitive DAC are used

to add and subtract fixed amounts of charge from the sampling

capacitor to bring the comparator back into a balanced condition.

When the comparator is rebalanced, the conversion is complete.

The control logic generates the ADC output code.

COMPARATOR

VIN

CONTROL LOGIC

CAPACITIVE

DAC

AGND

Ω

SW2

SW1

Figure 11. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding of the AD7475/AD7495 is straight binary.

The designed code transitions occur midway between successive

LSB integer values (that is, 1/2 LSB and 3/2 LSBs). The LSB size

is = VREF/4096. The ideal transfer characteristic for the

AD7475/AD7495 is shown in Figure 12.

111...111

111...110

111...000

011...111

000...010

000...001

000...000

0V 0.5LSB

VREF –1.5LSB

ANALOG INPUT

1LSB = VREF/4096

Figure 12. AD7475/AD7495 Transfer Characteristic

AD7475ARMZ 数据表(PDF) 13 Page - Analog Devices

AD7475ARMZ 数据表(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表下载