ADM3065EARMZ-R7 datasheet(11/27 Pages) AD

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Data Sheet

ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E

Rev. G | Page 11 of 27

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

RO 1

RE 2

DE 3

DI 4

VCC

GND

ADM3061E/

ADM3065E

TOP VIEW

(Not to Scale)

Figure 9. ADM3061E/ADM3065E 8-Lead Narrow Body SOIC_N

Pin Configuration

RO 1

RE 2

DE 3

DI 4

VCC

GND

ADM3061E/

ADM3065E

TOP VIEW

(Not to Scale)

Figure 10. ADM3061E/ADM3065E 8-Lead MSOP Pin Configuration

Table 8. ADM3061E/ADM3065E Pin Function Descriptions

Pin No.

Mnemonic

Description

Receiver Output Data. This output is high when (A − B) ≥ −30 mV and low when (A − B) ≤ −200 mV. This output is

tristated when the receiver is disabled, that is, when RE is driven high.

Receiver Enable Input. This is an active low input. Driving this input low enables the receiver and driving it high

disables the receiver.

Driver Enable. A high level on this pin enables the driver differential outputs, A and B. A low level places the driver

output into a high impedance state.

Transmit Data Input. Data to be transmitted by the driver is applied to this input.

GND

Ground.

Noninverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin A is

put into a high impedance state to avoid overloading the bus.

Inverting Driver Output and Receiver Input. When the driver is disabled, or when VCC is powered down, Pin B is put

into a high impedance state to avoid overloading the bus.

VCC

3.0 V to 5.5 V Power Supply. Adding a 0.1 μF decoupling capacitor between the VCC pin and the GND pin is recommended.

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