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ADM3065EBRMZ-R7 数据表(PDF) 7 Page - Analog Devices |
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ADM3065EBRMZ-R7 数据表(HTML) 7 Page - Analog Devices |
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7 / 27 page  Data Sheet ADM3061E/ADM3062E/ADM3063E/ADM3064E/ADM3065E/ADM3066E/ADM3067E/ADM3068E Rev. G | Page 7 of 27 TIMING SPECIFICATIONS ADM3061E/ADM3062E/ADM3063E/ADM3064E VCC = 3.0 V to 5.5 V, VIO = 1.62 V to VCC (ADM3062E/ADM3064E), TA = TMIN (−40°C) to TMAX (+125°C), unless otherwise noted. All typical specifications are at TA = 25°C, VIO = VCC = 3.3 V, unless otherwise noted. Table 4. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Maximum Data Rate1 500 kbps Propagation Delay tDPLH, tDPHL 220 800 ns RLDIFF capacitor = 54 Ω, CL1 capacitor = CL2 capacitor = 100 pF, see Figure 5 and Figure 40 Skew tDSKEW 5 100 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 40 Rise/Fall Times tDR, tDF 120 300 800 ns RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 40 Enable to Output High tDZH 100 1000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41 Enable to Output Low tDZL 100 1000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41 Disable Time from Low tDLZ 350 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41 Disable Time from High tDHZ 600 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41 Enable Time from Shutdown to High tDZH(SHDN)2 550 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41 Enable Time from Shutdown to Low tDZL(SHDN)2 550 2000 ns RL = 110 Ω, CL = 50 pF, see Figure 6 and Figure 41 RECEIVER Maximum Data Rate 500 kbps Propagation Delay tRPLH, tRPHL 200 ns CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and Figure 42 Skew/Pulse Width Distortion tRSKEW 50 ns CL = 15 pF, |VID| ≥ 1.5 V, VCM = 1.5 V, see Figure 7 and Figure 42 Enable to Output High tRZH 10 50 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8 and Figure 44 Enable to Output Low tRZL 10 50 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, DE high, see Figure 8 and Figure 44 Disable Time from Low tRLZ 10 50 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 44 Disable Time from High tRHZ 10 50 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 44 Enable from Shutdown to High tRZH(SHDN)3 2000 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 43 Enable from Shutdown to Low tRZL(SHDN)3 2000 ns RL = 1 kΩ, CL = 15 pF, |VID| ≥ 1.5 V, see Figure 8 and Figure 43 TIME TO SHUTDOWN tSHDN4 40 ns 1 Maximum data rate assumes a ratio of tDR:tBIT:tDF equal to 1:0.5:1. 2 tDZH(SHDN) and tDZL(SHDN) refer to the time for the device to enable when DE changes from 0 V to VCC. RE = VCC for this condition. 3 tRZH(SHDN) and tRZL(SHDN) refer to the time for the device to enable when RE changes from VCC to 0 V. DE = 0 V for this condition. 4 Minimum time required to put the device into shutdown: DE and RE must be disabled for more than 40 ns for the device to go into shutdown. |
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