ADM7154

Data Sheet

Rev. B | Page 14 of 23

THEORY OF OPERATION

The ADM7154 is an ultralow noise, high power supply rejection

ratio (PSRR) linear regulator targeting radio frequency (RF)

applications. The input voltage range is 2.3 V to 5.5 V, and it can

deliver up to 600 mA of load current. Typical shutdown current

consumption is 0.2 µA at room temperature.

Optimized for use with 10 µF ceramic capacitors, the ADM7154

provides excellent transient performance.

VREG

GND

VOUT

VIN

EN

REF

REF_SENSE

REFERENCE

SHUTDOWN

ACTIVE

RIPPLE

FILTER

CURRENT-LIMIT,

THERMAL

PROTECT

OTA

BYP

Figure 42. Simplified Internal Block Diagram

Internally, the ADM7154 consists of a reference, an error

amplifier, and a P-channel MOSFET pass transistor. Output

current is delivered via the PMOS pass device, which is

controlled by the error amplifier. The error amplifier compares

the reference voltage with the feedback voltage from the output

and amplifies the difference. If the feedback voltage is lower

than the reference voltage, the gate of the PMOS device is

pulled lower, allowing more current to pass and increasing the

output voltage. If the feedback voltage is higher than the

reference voltage, the gate of the PMOS device is pulled higher,

allowing less current to pass and decreasing the output voltage.

By heavily filtering the reference voltage, the ADM7154 is able

to achieve 1.5 nV/√Hz output typical from 10 kHz to 1 MHz.

Because the error amplifier is always in unity gain, the output

noise is independent of the output voltage.

To maintain very high PSRR over a wide frequency range, the

ADM7154 architecture uses an internal active ripple filter. This

stage isolates the low output noise LDO from noise on the VIN

pin. The result is that the PSRR of the ADM7154 is significantly

higher over a wider frequency range than any single stage LDO.

The ADM7154 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. When EN is high,

VOUT turns on, and when EN is low, VOUT turns off. For

automatic startup, tie EN to VIN.

VREG

VIN

REF_SENSE

REF

VOUT

BYP

GND

EN

7V

4V

4V

4V

4V

4V

4V

4V

4V

7V

7V

Figure 43. Simplified ESD Protection Block Diagram

The ESD protection devices are shown in the block diagram as

Zener diodes (see Figure 43).