ADE7978ACPZ datasheet(90/125 Pages) AD

90 / 125 page

ADE7978/ADE7933/ADE7932/ADE7923

Data Sheet

Rev. D | Page 90 of 125

If only two or three ADE7933/ADE7932/ADE7923 devices are

used, the DATA_B and/or DATA_N pins are connected to VDD.

The waveform samples computed by the ADE7978 that correspond

to these unconnected ADE7933/ADE7932 devices are set to full

scale. After passing through the high-pass filter, the waveform

samples are set to 0, and all quantities computed by the ADE7978

using these samples are 0.

Bits[5:4] (CONSEL[1:0]) in the ACCMODE register

(Address 0xE701) determine the way that the phase powers are

computed in the ADE7978, based on the meter configuration.

For more information, see the Energy Accumulation Modes

section.

The ADE7933/ADE7932/ADE7923 receive a 4.096 MHz clock at

the XTAL1 pin from the ADE7978 CLKOUT pin; the XTAL2 pins

of the ADE7933/ADE7932 and ADE7923 are left open. Do not

clock the ADE7933/ADE7932 or ADE7923 using a crystal

connected between the XTAL1 and XTAL2 pins because the

ADE7933/ADE7932/ADE7923 devices must function synchro-

nously with the ADE7978; using the CLKOUT clock of the

ADE7978 ensures this synchronization.

The ADE7978 RESET_EN pin is connected to the RESET_EN

pins of all ADE7933/ADE7932 and ADE7923 devices in the

system. The ADE7978 VT_A, VT_B, VT_C, and VT_N pins are

connected to the corresponding V2/TEMP pin of each ADE7933/

ADE7932/ADE7923 in the system. For example, the VT_A pin

of the ADE7978 is connected to the V2/TEMP pin of the

ADE7933/ADE7932 that monitors Phase A. If the schematic

does not monitor certain phases, leave the corresponding VT_x

pin of the ADE7978 unconnected. For example, the meter in the

configuration shown in Figure 113 does not monitor Phase B or the

neutral current. Therefore, the VT_B and VT_N pins are left open.

When the RESET pin of the ADE7978 is set low for at least

10 µs and then brought high again, the RESET_EN pin is set

low, and the VT_A, VT_B, VT_C, and VT_N pins toggle eight

times from high to low at a frequency of 4.096 MHz, resetting

the ADE7933/ADE7932/ADE7923 devices. When the RESET_EN,

VT_A, VT_B, VT_C, and VT_N pins are set high again, the reset

of the ADE7933/ADE7932 and ADE7923 devices ends (see the

Hardware Reset section for more information).

The VT_A, VT_B, VT_C, and VT_N pins of the ADE7978 select

the signal measured by the V2 voltage ADC of the ADE7933

and ADE7923: either the second voltage input or the internal

temperature sensor. (The ADE7932 always measures the internal

temperature sensor.) If the VT_x signal is low, the ADC measures

the input signal at the V2P pin. If the VT_x signal is high, the

ADC measures the internal temperature sensor.

The ADE7978 reads the outputs of the ADE7933/ADE7932 and

ADE7923 using a bit stream communication composed of two

signals, SYNC and DATA. The SYNC pin of the ADE7978 is

connected to the SYNC pin of each ADE7933/ADE7932 and

ADE7923 device. The DATA pin of each ADE7933/ADE7932

and ADE7923 is connected to the corresponding DATA_x pin of

the ADE7978 (x = A, B, C, or N). For example, the DATA pin of

the Phase A ADE7933/ADE7932 is connected to the DATA_A

pin of the ADE7978.

If the schematic does not monitor certain phases, connect the

corresponding DATA_x pin of the ADE7978 to VDD. For

example, the meter in the configuration shown in Figure 113

does not monitor Phase B or the neutral current. Therefore, the

DATA_B and DATA_N pins of the ADE7978 are tied to VDD.

The SYNC pin of the ADE7978 generates a 1.024 MHz serial clock

to the ADE7933/ADE7932 and ADE7923 slaves. Each

ADE7933/ADE7932 and ADE7923 responds with a bit stream

generated by the first stage of the ADE7933/ADE7932 and

ADE7923 ADCs (see the Bit Stream Communication Between

the ADE7978 and the ADE7933/ADE7932 and ADE7923

section).

ADE7978 QUICK SETUP AS AN ENERGY METER

An energy meter is usually characterized by the nominal current

(In), nominal voltage (Vn), nominal frequency (fn), and the meter

constant (MC). To quickly set up the ADE7978, follow these steps:

1. If fn = 60 Hz, set Bit 14 (SELFREQ) to 1 in the COMPMODE

bit at 0, the default value.

2. Initialize the CF1DEN, CF2DEN, and CF3DEN registers

(Address 0xE611 to Address 0xE613) based on the following

equation:

CFxDEN

]

imp/kwh

[

103

For more information, see the Energy-to-Frequency

Conversion section.

3. Initialize the WTHR, VARTHR, and VATHR registers

(Address 0xEA02 to Address 0xEA04) based on the

following equation:

WTHR, VARTHR, and VATHR =

3600

PMAX

For more information, see the Active Energy Calculation

section, the Reactive Energy Calculation, and the Apparent

Energy Calculation section.

4. Initialize the VLEVEL register (Address 0x43A2) based on

the following equation:

VLEVEL = VFS/Vn × 4 × 106

For more information, see the Fundamental Active Power

Calculation section.

5. Initialize the VNOM register based on the following equation:

VNOM = V/VFS × 3,761,808

For more information, see the Apparent Power Calculation

Using VNOM section.

ADE7978ACPZ 数据表(PDF) 90 Page - Analog Devices

ADE7978ACPZ 数据表(HTML) 90 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载