3

Maxim Integrated

with Display Hold

MAX136

Detailed Description

The MAX136 3½ digit ADC is similar to the Maxim

ICL7136 except for the addition of a Hold pin. For a

detailed product description, and applications informa-

tion (other than the operation of the Hold pin described

below), refer to Maxim's ICL7136 data sheet.

Hold Input

The Hold input is a digital input with a logic thresh-

old approximately midway between V+ and Test. The

MAX136 continuously performs conversions, indepen-

dent of the Hold input. When the Hold input is at V+ the

display latch pulse is inhibited, and the display latches

are not updated; when the Hold input is low or at the

Test voltage, the display is updated at the end of each

conversion. The MAX136 maintains low-power dissipa-

tion even during display hold by eliminating the pulldown

resistor between Hold and Test present on the ICL7116.

The Hold input is CMOS compatible, and can also be

driven by a switch connected between Test and V+

(Figure 1).

Reference Input

Unlike the ICL7136, the MAX136 does not have a refer-

ence low input. Apply the reference voltage between

Reference High (REF HI) and

Figure 1. MAX136 Typical Operating Circuit, 200mV Full Scale

Figure 2. MAX136 Typical Operating Circuit, 2.0V Full Scale

MAX136

ANALOG

INPUT

9V

TO ANALOG

COMMON (P32)

LCD DISPLAY

BACKPLANE

DRIVE

SEGMENT

DRIVE

0.47µF

C+ REF

C- REF

0.47µF

0.01µF

0.047µF

1MI

180kI

180kI

150kI

100kI

31

34

33

20

21 MINUS SIGN

RUN

HOLD

37

35

36

26

1

IN HI

2-19

22-25

PDL

BP

TEST

HOLD

REF HI

V+

V-

IN LO

COMMON

BUFF

A/Z

INT

30

32

28

29

39

38

40

50pF

27

MAX136

ANALOG

INPUT

9V

TO ANALOG

COMMON (P32)

LCD DISPLAY

BACKPLANE

DRIVE

SEGMENT

DRIVE

0.47µF

C+ REF

C- REF

0.47µF

0.01µF

0.047µF

1MI

180kI

180kI

150kI

100kI

31

34

33

20

21 MINUS SIGN

RUN

HOLD

37

35

36

26

1

IN HI

2-19

22-25

PDL

BP

TEST

HOLD

REF HI

V+

V-

IN LO

COMMON

BUFF

A/Z

INT

30

32

28

29

39

38

40

50pF

27