ADL5354

Data Sheet

Rev. A | Page 6 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VGS0

VGS1

VGS2

LOSW

PWDN

VPOS

COMM

LOI2

LOI1

MNIN

MNCT

COMM

DVIN

VPOS

COMM

VPOS

COMM

DVCT

ADL5354

TOP VIEW

(Not to Scale)

NOTES

1. NIC = NO INTERNAL CONNECTION.

2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND.

1

2

3

4

5

6

7

8

9

27

26

25

24

23

22

21

20

19

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

MNIN

RF Input for Main Channel. Internally matched to 50 Ω. Must be ac-coupled.

2

MNCT

Center Tap for Main Channel Input Balun. Bypass to ground using low inductance capacitor.

3, 5, 7, 12, 20, 34

COMM

Device Common (DC Ground).

4, 6, 10, 16, 21, 30, 36

VPOS

Positive Supply Voltage.

8

DVCT

Center Tap for Diversity Channel Input Balun. Bypass to ground using low inductance capacitor.

9

DVIN

RF Input for Diversity Channel. Internally matched to 50 Ω. Must be ac-coupled.

11

DVGM

Diversity Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation.

13, 14

DVOP, DVON

Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled up to

VCC using external inductors, see Figure 53 for details.

15

DVLE

Diversity Channel IF Return. This pin must be grounded.

17

DVLG

Diversity Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation.

18, 28

NIC

No Internal Connection. Do not connect to this pin.

19

LOI1

Local Oscillator Input 1. Internally matched to 50 Ω. Must be ac-coupled.

22

PWDN

Power Down. Connect this pin to ground for normal operation. Connect pin to 3 V for disable

mode when using VPOS ≤ 3.6 V. PWDN pin must be grounded when VPOS > 3.6 V.

23

LOSW

Local Oscillator Input Selection Switch. Set LOSW high to select LOI1 or set LOSW low to select LOI2.

24, 25, 26

VGS0, VGS1,

VGS2

Gate to Source Control Voltages. For typical operation, set VGS0, VGS1, and VGS2 to a low logic

level.

27

LOI2

Local Oscillator Input 2. Internally matched to 50 Ω. Must be ac-coupled.

29

MNLG

Main Channel LO Buffer Bias Setting. Connect a 1 kΩ resistor to ground for typical operation.

31

MNLE

Main Channel IF Return. This pin must be grounded.

32, 33

MNOP, MNON

Main Channel Differential Open-Collector Outputs. Pull up MNOP and MNON to VCC by using

external inductors, see Figure 53 for details.

35

MNGM

Main Amplifier Bias Setting. Connect a 1.3 kΩ resistor to ground for typical operation.

EPAD

Exposed Pad. The exposed pad must be connected to ground.