All trademarks are property of their respective owners.

www.diodes.com

1/18/2017

2016-11-0004

PT0493-4

28

PI5USB2546

Thermal Sense

The PI5USB2546 protects itself with thermal sensing circuit that monitor the operating temperature of the power distribution

switch and disables operation if the temperature exceeds recommended operating conditions. The device operates in constant-

current mode during an over-current condition, which increases the voltage drop across power switch. The power dissipation in

the package is proportional to the voltage drop across the power switch, so the junction temperature rises during an over-current

condition. The thermal sensor turns off the power switch when the die temperature exceeds 135°C regardless of whether the

power switch is in current limit. Hysteresis is built into thermal sensor, and the switch turns on after the device has cooled by

approximately 20°C. The switch continues to cycle off and on until the fault is removed. The open-drain false reporting output

/FAULT is asserted (active low) when an over-temperature shutdown condition.

Application Information

Input and Output Capacitance

Input and output capacitance improves the performance of the device; the actual capacitance should be optimized for the particular

application. For all applications, a 0.1uF or greater ceramic bypass capacitor between IN and GND is recommended as close to the

device as possible for local noise decoupling. This precaution reduces ringing on the input due to power-supply transients.

Additional input capacitance may be needed on the input to reduce voltage overshoot from exceeding the absolute-maximum

voltage of the device during heavy transient conditions or output shorting. This is especially important during bench testing when

long inductive cables are used to connect the evaluation board to the bench power supply. Normally suggested the distance

between IC and DC supply is less than 15cm.

Output capacitance also need to be close to IC as possible. When large transient currents are expected on the output，placing a

high-value electrolytic capacitor on the output pin is recommended,

Layout Design Guideline

1.

The PCB is suggested to use at least 4 layers

2.

The high speed differential pair should be maintain 90Ω

3.

Do not route the high speed signal over any split plane

4.

Minimized the number of vias and corners on the high speed trace for reducing the signal reflections and impedance

changes

5.

If it’s necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This can reduces reflections on

the signal by minimizing impedance discontinuities.

6.

The high speed trace should be routed symmetrically and parallelism (including the test points on the high speed trace).

The non-parallelism trace will cause the impedance discontinuities and affect the signal quality

7.

Avoid any unnecessary stubs on the differential pair. The stubs will introduce the signal reflections which affect the signal

quality

8.

Avoid routing the high speed differential pair under the crystal, oscillator, clock synthesizer, magnetic devices or ICs to

cause the interference.

9.

Avoid anti-etch on the GND plane