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71M6543GHT 数据表(PDF) 60 Page - Maxim Integrated Products |
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71M6543GHT 数据表(HTML) 60 Page - Maxim Integrated Products |
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60 / 75 page  Maxim Integrated │ 60 71M6543FT/71M6543HT/ 71M6543GT/71M6543GHT Energy Meter ICs www.maximintegrated.com Table 13. I/O RAM Locations in Alphabetical Order (continued) NAME LOCATION RSTWK DIR DESCRIPTION RTC_THR[4:0] 289F[4:0] 0 – R/W Thetargethoursregister.TheRTC_TinterruptoccurswhenRTC_MINbecomesequaltoRTC_TMINandRTC_HR becomesequaltoRTC_THR. RTC_WR 2890[7] 0 0 R/W Freezes the RTC shadow register so it is suitable for MPU writes. When RTC_WR is cleared, the contents of the shadow register are written to the RTC counter on the next RTC clock (~500 Hz). When RTC_WR is read, it returns 1 as long as RTC_WR is set. It continues to return one until the RTC counter actually updates. RTC_SEC[5:0] RTC_MIN[5:0] RTC_HR[4:0] RTC_DAY[2:0] RTC_DATE[4:0] RTC_MO[3:0] RTC_YR[7:0] 2893[5:0] 2894[5:0] 2895[4:0] 2896[2:0] 2897[4:0] 2898[3:0] 2899[7:0] – – – – – – – – – – – – – – R/W The RTC interface registers. These are the year, month, day, hour, minute and second parameters for the RTC. The RTCissetbywritingtotheseregisters.Year00andallothersdivisibleby4aredefinedasaleapyear. SEC 00 to 59 MIN 00 to 59 HR 00 to 23 (00 = Midnight) DAY 01 to 07 (01 = Sunday) DATE 01 to 31 MO 01 to 12 YR 00 to 99 Each write operation to one of these registers must be preceded by a write to 0x20A0. RTM_E 2106[1] 0 0 R/W Real Time Monitor enable. When 0, the RTM output is low. RTM0[9:8] RTM0[7:0] RTM1[7:0] RTM2[7:0] RTM3[7:0] 210D[1:0] 210E[7:0] 210F[7:0] 2110[7:0] 2111[7:0] 0 0 0 0 0 0 0 0 0 0 R/W Four RTM probes. Before each CE code pass, the values of these registers are serially output on the RTM pin. The RTM registers are ignored when RTM_E = 0. Note that RTM0 is 10 bits wide. The others assume the upper two bits are 00. SBASE:[10:0] 2519[2:0] 251A[7:0] 0 0 R/W Base temperature for limit checking SECURE SFR B2[6] 0 0 R/W Inhibitserasureofpage0andflashaddressesabovethebeginningofCEcodeasdefinedbyCE_LCTN[6:0]for 71M6543GT/GHTandCE_LCTN[5:0]for71M6543FT/HT.AlsoinhibitsthereadofflashviatheSPIandICEport. SFILT 251D[3:0] 0 0 R/W Filter variable for wake on temperature extremes. SLEEP 28B2[7] 0 0 W Puts the part to SLP mode. Ignored if system power is present. The part wakes when the Wake timer expires, when push button is pushed, or when system power returns. SLOT_EXT[3:0] 2112[3:0] 0 0 R/S If non-zero, will extend the duration of time slot zero by up to 15 extra crystal cycles. The ADC result for time slot zerowillbeleft-shiftedninebitsifSLOT_EXT=0andfourbitsifSLOT_EXT≠0. SMAX[6:0] 251B[6:0] 0 0 R/W Maximum temperature for limit checking SMIN[6:0] 251C[6:0] 0 0 R/W Minimum temperature for limit checking SPI_CMD[7:0] SFR FD[7:0] – – R SPI command register for the 8-bit command from the bus master. SPI_E 270C[4] 1 1 R/W SPIportenable.EnablesSPIinterfaceonpinsSEGDIO36–SEGDIO39.RequiresthatLCD_MAP[36-39]=0. SPI_SAFE 270C[3] 0 0 R/W Limits SPI writes to SPI_CMD and a 16-byte region in DRAM. No other writes are permitted. SPI_STAT[7:0] 2708[7:0] 0 0 R SPI_STAT contains the status results from the previous SPI transaction. Bit 7: Ready error: The 71M654xT was not ready to read or write as directed by the previous command. Bit 6: Read data parity: This bit is the parity of all bytes read from the 71M654xT in the previous command. Does not include the SPI_STAT byte. Bit 5: Write data parity: This bit is the overall parity of the bytes written to the 71M654xT in the previous command. It includes CMD and ADDR bytes. Bit 4-2: Bottom 3 bits of the byte count. Does not include ADDR and CMD bytes. One, two, and three byte instructions return 111. Bit 1: SPI FLASH mode: This bit is zero when the TEST pin is zero. Bit0:SPIFLASHmodeready:UsedinSPIFLASHmode.Indicatesthattheflashisreadytoreceiveanotherwrite instruction. STEMP[15:0] 2881[7:0] 2882[7:0] – – R The result of the temperature measurement. SUM_SAMPS[12:8] SUM_SAMPS[7:0] 2107[4:0] 2108[7:0] 0 0 R/W The number of multiplexer cycles per XFER_BUSY interrupt. Maximum value is 8191 cycles. TC_A[9:0] 2508[1:0] 2509[7:0] 0 0 R/W Temperaturecompensationfactorforquadraticcompensation. TC_B[11:0] 250A[3:0] 205B[7:0] 0 0 R/W Temperaturecompensationfactorforquadraticcompensation. TC_C[11:0] 289C[3:0] 289D[7:0] 0 0 R/W Temperaturecompensationfactorforquadraticcompensation. TEMP_22[12:8] TEMP_22[7:0] 230A[4:0] 230B[7:0] 0 – R Storage location for STEMP at 22NC. STEMP is an 11-bit word. |
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