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71M6543GHT-IGT/F 数据表(PDF) 29 Page - Maxim Integrated Products |
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71M6543GHT-IGT/F 数据表(HTML) 29 Page - Maxim Integrated Products |
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29 / 75 page  Maxim Integrated │ 29 71M6543FT/71M6543HT/ 71M6543GT/71M6543GHT Energy Meter ICs www.maximintegrated.com Table 6. Special Function Register Map Special Function Registers Only a few addresses in the SFR memory space are occupied; other addresses are unimplemented. A read access to unimplemented addresses returns undefined data, while a write access has no effect. SFRs specific to the 71M654xT are shown in bold print on a shaded field. The registers at 0x80, 0x88, 0x90, etc., are bit address- able, all others are byte addressable. Timers and Counters The 71M6543FT/HT/GT/GHT contains two 16-bit timer/ counter registers: Timer 0 and Timer 1. These registers can be configured for counter or timer operations. In timer mode, the register is incremented every machine cycle, i.e., it counts up once for every 12 periods of the MPU clock. In counter mode, the register is incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins, see 2.5.8 Digital I/O). Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clockfrequency(CKMPU).Therearenorestrictionson the duty cycle, however to ensure proper recognition of the 0 or 1 state, an input should be stable for at least 1 machine cycle. Four operating modes can be selected for Timer 0 and Timer 1. The TMOD register is used to select the appro- priate mode. The timer/counter operation is controlled by the TCON register. Bits TR1 and TR0 in the TCON regis- ter start their associated timers when set. Table 7. Timers/Counters Mode Description HEX/ BIN BIT ADDRESSABLE BYTE ADDRESSABLE BIN/ HEX X000 X001 X010 X011 X100 X101 X110 X111 F8 INTBITS VSTAT RCMD SPI_CMD FF F0 B F7 E8 IFLAGS EF E0 A E7 D8 WDCON DF D0 PSW D7 C8 T2CON CF C0 IRCON C7 B8 IEN1 IP1 S0RELH S1RELH PDATA BF B0 P3 (DIO12:15) FLSH_CTL FLSH_ BANK FLSH_ PGADR B7 A8 IEN0 IP0 S0RELL AF A0 P2 (DIO8:11) A7 98 S0CON S0BUF IEN2 S1CON S1BUF S1RELL EEDATA EECTRL 9F 90 P1(DIO4:7) DPS FLSH_ ERASE 97 88 TCON TMOD TL0 TL1 TH0 TH1 CKCON 8F 80 P0 (DIO0:3) SP DPL DPH DPL1 DPH1 PCON 87 M1 M0 MODE FUNCTION 0 0 Mode 0 13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 register and the remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1, respectively). The 3 high order bits of TL0 and TL1 are held at zero. 0 1 Mode 1 16-bit Counter/Timer mode. 1 0 Mode 2 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1, while TL0 or TL1 is incremented everymachinecycle.WhenTLxoverflows,avaluefromTHxiscopiedtoTLx. 1 1 Mode 3 If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent 8-bit Timer/Counters. |
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