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ADP1031ACPZ-1-R7 数据表(PDF) 11 Page - Analog Devices |
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ADP1031ACPZ-1-R7 数据表(HTML) 11 Page - Analog Devices |
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11 / 38 page  Data Sheet ADP1031 Rev. A | Page 11 of 38 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 1 NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. EPGNDP IS INTERNALLY CONNECTED TO PGNDP, EPGNDM IS INTERNALLY CONNECTED TO MGND, AND EPGND2 IS INTERNALLY CONNECTED TO SGND. ADP1031 MI 2 MSS 3 MGND TOP VIEW (Not to Scale) 4 SGND2 5 SGND1 6 SSS 7 SO DNC 25 DNC 26 DNC 27 SGND2 28 PGNDP 29 SWP 30 VINP FP M EPGNDM EPGND2 EPGNDP S Figure 3. Pin Configuration Table 9. Pin Function Descriptions Pin No. Mnemonic Isolation Domain Direction Description 1 MI Master Output SPI Data Output from the Slave MI and SO Line. This pin is paired with SO. On the slave domain, SO drives this pin. 2 MSS Master Input SPI Slave Select Input from the Master Controller. This pin is paired with SSS. On the slave domain, this pin drives SSS. This signal uses an active low logic. 3 MGND Master Return Master Domain Signal Ground Connection. 4 SGND2 Slave Return Slave Domain Ground Connection. This pin can be left unconnected. 5 SGND1 Slave Return Slave Domain SPI Isolator Ground. 6 SSS Slave Output SPI Slave Select Output. This pin is paired with MSS. On the master domain, MSS drives this pin. 7 SO Slave Input SPI Data Input Going to the Master MI and SO Line. This pin is paired with MI. On the master domain, this pin drives MI. 8 SI Slave Output SPI Data Output from the Master MO and SI Line. This pin is paired with MO. On the master domain, MO drives this pin. 9 SCK Slave Output SPI Clock Output from the Master. This pin is paired with MCK. On the master domain, MCK drives this pin. 10 SVDD1 Slave Power SPI Isolator Power Supply. Connect a 100 nF decoupling capacitor from SVDD1 to SGND1. 11 FB3 Slave Not applicable Inverting Regulator Feedback Pin. 12 VOUT3 Slave Power Inverting Regulator Output and Overvoltage Sense. 13 SW3 Slave Not applicable Inverting Regulator Switch Node. 14 SYNC Slave Input SYNC Pin. To synchronize the switching frequency, connect the SYNC pin to an external clock at twice the required switching frequency. Do not leave this pin floating. Connect a 100 kΩ pull-down resistor to SGND2. 15 VOUT2 Slave Power Buck Regulator Output Feedback. 16 SGND2 Slave Return Slave Power Ground. Ground return for inverting and buck regulator output capacitors. 17 SW2 Slave Not applicable Buck Regulator Switch Node. 18 VOUT1 Slave Power Flyback Regulator Output and Overvoltage Sense. This pin is the input to the buck and inverting regulators. 19 FB1 Slave Feedback Node for the Flyback Regulator. 20 SVDD2 Slave Power GPIO Isolators Power Supply. Connect a 100 nF decoupling capacitor from SVDD2 to SGND2. |
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