ADP1031ACPZ-5-R7 datasheet(37/38 Pages) AD

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Data Sheet

ADP1031

Rev. A | Page 37 of 38

PCB LAYOUT CONSIDERATIONS

To achieve optimum efficiency, proper regulation, strong

stability, and low noise, a well designed PCB layout is required.

Follow these guidelines when designing PCBs:

•

Keep the input bypass capacitor, CIN, close to the VINP pin

and the PGNDP pin.

•

Keep the high current switching paths as short as possible.

These paths include the connections between the

following:

•

CIN, VINP, the primary winding of the transformer,

and PGNDP

•

VOUT1, CFLYBK, Diode 1 (D1), the secondary winding

of the transformer, and SGND2

•

VOUT2, SW2, Inductance 1 (L1), CBUCK, and SGND2

•

VOUT3, SW3, Inductance 2 (L2), CINV, and SGND2

•

Keep high current traces as short and wide as possible to

minimize parasitic series inductance, which causes spiking

and EMI.

•

Avoid routing high impedance traces near any node

connected to the SWP, SW2, and SW3 pins or near the L1

and L2 inductors or the T1 transformer to prevent radiated

switching noise injection.

•

Place the feedback resistors as close to the FB1 and FB3

pins as possible to prevent high frequency switching noise

injection.

•

To minimize EMI, place the MVDD decoupling capacitor

(C1) as close to the MVDD pin (Pin 39) and the MGND pin

(Pin 3).

•

To minimize EMI, place the SVDD1 decoupling capacitor

(C3) as close to the SVDD1 pin (Pin 10) and the SGND1

pin (Pin 5), and place the SVDD2 decoupling capacitor

(C7) as close to the SVDD2 pin (Pin 20) and the SGND2

pin (Pin 16).

Figure 77 shows a suggested top layer layout for the ADP1031.

CIN

CINV

VOUT1

VOUT2

VOUT3

VINP

PGNDP

CBUCK

CFLYBK

18.8mm

R10

MVDD

Figure 77. Suggested Top Layer Layout

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