ADP2503ACPZ-2.8-R7 datasheet(11/16 Pages) AD

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Data Sheet

ADP2503/ADP2504

Rev. D | Page 11 of 16

THEORY OF OPERATION

BAND GAP

REFERENCE

SYNC

PGND

AGND

PVIN

VBAT = 2.3V

TO 5.5V

VIN

VOUT

SW1

SW2

1.5µH

2.25V

UVLO

10µF

22µF

ADP2503/ADP2504

BIASING

ADP2503/ADP2504

PMOS1

PMOS2

NMOS1

NMOS2

THERMAL

PROTECTION

PWM CONTROL

OSCILLATOR

–0.5V

SOFT START

Figure 29. ADP2503/ADP2504 Block Diagram

The ADP2503/ADP2504 are synchronous average current-mode

switching buck-boost regulators designed to maintain a fixed

output voltage VOUT from an input supply VIN that can be

greater than, equal to, or less than VOUT. When VIN is signifi-

cantly greater than VOUT, the device is in buck mode: PMOS2 is

always active, NMOS2 is always off, and the PMOS1 and NMOS1

switches constitute a buck converter. When VIN is significantly

lower than VOUT, the device is in boost mode: PMOS1 is always

active, NMOS1 is always off, and the NMOS2 and PMOS2

switches constitute a boost converter. When VIN is in the range

[VOUT ± 10%], the ADP2503/ADP2504 automatically enter the

buck-boost mode. In buck-boost mode, the two operations,

buck (PMOS1 and NMOS1 switching in antiphase) and boost

(NMOS2 and PMOS2 switching in antiphase), take place at each

period of the clock. This is aimed at maintaining the regulation

and keeping a minimal current ripple in the inductor to guaran-

tee good transient performances.

POWER SAVE MODE

When the SYNC pin is low, the ADP2503/ADP2504 can operate

in power save mode (PSM). In this mode, when the load current

becomes less than 75 mA nominally at VIN = 3.6 V, the control-

ler pulls up VOUT and then halts the switching regime until VOUT

goes back to a restart value. Then VOUT is pulled up again for a

new cycle. This minimizes the switching losses at light load. When

the load rises above 150 mA, the ADP2503/ADP2504 revert to

fixed PWM mode. This results in about 75 mA of hysteresis

between PSM and fixed PWM, preventing oscillations between

these two modes.

SOFT START

When the ADP2503/ADP2504 are started, VOUT is ramped from

0 V to its final programmed value in 200 μs (typical). This limits

the inrush current to less than 600 mA for a nominal output

capacitor of 20 μF. Because the VOUT start-up slope is constant,

the inrush current becomes larger if the output capacitor is

made larger.

SYNC FUNCTION

When the SYNC pin is high, PSM is deactivated. The ADP2503/

ADP2504 always operate in PWM using the internal oscillator.

When the SYNC pin is switching in the 2.1 MHz to 2.9 MHz

range, the regulator switching frequency slides to the frequency

applied on SYNC and then locks on it. When the SYNC pin

stops switching, the regulator switching frequency slides back to

the internal oscillator frequency.

ENABLE

The device starts operation with soft start when the EN pin

is brought high. Pulling the EN pin low forces the device into

shutdown, with a typical shutdown current of 0.2 μA.

In this mode, the PMOS power switches are turned off, the

NMOS power switches are turned on, and the control circuitry

is not enabled. For proper operation, the EN pin must be

terminated and must not be left floating.

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