Data Sheet

ADP172

APPLICATIONS INFORMATION

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Rev. F | 12 of 17

CAPACITOR SELECTION

Output Capacitor

The ADP172 is designed for operation with small, space-saving ce-

ramic capacitors but functions with most commonly used capacitors

as long as care is taken with the effective series resistance (ESR)

value. The ESR of the output capacitor affects the stability of the

LDO control loop. A minimum of 1 µF capacitance with an ESR of

1 Ω or less is recommended to ensure the stability of the ADP172.

The transient response to changes in load current is also affected

by output capacitance. Using a larger value of output capacitance

improves the transient response of the ADP172 to large changes in

load current. Figure 24 and Figure 25 show the transient responses

for output capacitance values of 1 µF and 4.7 µF, respectively.

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN to GND reduces the circuit

sensitivity to the printed circuit board (PCB) layout, especially when

long input traces or high source impedance is encountered. If

greater than 1 µF of output capacitance is required, increase the

input capacitor to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitor can be used with the ADP172,

as long as it meets the minimum capacitance and maximum ESR

requirements. Ceramic capacitors are manufactured with a variety

of dielectrics, each with different behavior over temperature and

applied voltage. Capacitors must have a dielectric adequate to

ensure the minimum capacitance over the necessary temperature

range and dc bias conditions. An X5R or X7R dielectric with a

voltage rating of 6.3 V or 10 V is recommended. The Y5V and Z5U

dielectrics are not recommended due to their poor temperature and

dc bias characteristics.

Figure 26 depicts the capacitance vs. bias voltage characteristics

of a 0402, 1 µF, 10 V X5R capacitor. The variance of a capacitor

is strongly influenced by the capacitor size and voltage rating. In

general, a capacitor in a larger package or with a higher voltage

rating exhibits less capacitance variance over bias voltage. The

temperature variation of the X5R dielectric is about ±15% over the

−40°C to +85°C temperature range and is not a function of package

or voltage rating.

Figure 26. Capacitance vs. Bias Voltage Characteristics

Use Equation 1 to determine the worst case capacitance, account-

ing for capacitor variation over temperature, component tolerance,

and voltage.

where:

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO)

over −40°C to +85°C is assumed to be 15% for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10%, and

Substituting these values in Equation 1 yields

Therefore, the capacitor chosen in this example meets the mini-

mum capacitance requirement of the LDO over temperature and

tolerance at the chosen output voltage.

To guarantee the performance of the ADP172, it is imperative that

the effects of dc bias, temperature, and tolerances on the behavior

of the capacitors be evaluated for each application.