FS32K116LEX0MLFT datasheet(39/101 Pages) NXP

39 / 101 page

Table 28. External System Oscillator frequency specifications

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

S32K14x/

S32K14xW

S32K11x

S32K14x/

S32K14xW

S32K11x

S32K14x/

S32K14xW

S32K11x

fosc_hi

Oscillator crystal or resonator

frequency

—

40 1, 2

MHz

fec_extal

Input clock frequency (external clock

mode)

—

MHz

3, 2, 4

tdc_extal

Input clock duty cycle (external clock

mode)

3, 2, 4

tcst

Crystal Start-up Time

8 MHz low-gain mode (HGO=0)

—

1.5

—

8 MHz high-gain mode (HGO=1)

—

2.5

—

40 MHz low-gain mode (HGO=0)

—

40 MHz high-gain mode (HGO=1)

—

For an ideal clock of 40 MHz, if permitted by application requirements, an error of +/- 5% is supported with 50% duty cycle.

(S32K14xW) At 40 MHz to 36 MHz when sourcing for ADC clock please use divider ADCn.ADC_CFG1[ADICLK] to ½ or lower for the specific ADC instance. This

will help achieve duty cycle requirement. For 36 MHz and 32 MHz 45-55% or better duty cycle to be maintained. For frequencies lower than 32 MHz, please

maintain duty cycle of 40-50% or better.

S32K1xx : Frequencies below 40 MHz can be used for degraded duty cycle upto 40-60%. When using for ADC clock further restrictions apply. At 50 MHz to 45

MHz when sourcing for ADC clock please use divider ADCn.ADC_CFG1[ADICLK] to ½ or lower for the specific ADC instance. This will help achieve duty cycle

requirement. for 45 MHz and 41 MHz 45-55% or higher duty cycle should be maintained.

(S32K14xW) The limits to source ADC clock are 40 MHz, so in cases the input clock is higher than 40 MHz, it cannot be used as a source of ADC clock.

Proper PC board layout procedures must be followed to achieve specifications.

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