SP8531DS/01

SP8531 12-Bit Sampling Serial Out Analog to Digital Converter

© Copyright 1999 Sipex Corporation

11

Communication to DSP TMS320C26 in

Free-Run

To use free-run mode the chip select on the

SP8531 must be low and is therefore tied to

ground. Since status gives a low pulse before the

start of conversion, this signal is used to provide

the necessary Frame Sync Receive (FSR) pulse

to start reading the data. All it needs is an

inverter to provide for the correct logic level.

CLK

SCLK

CS

STATUS

SP8531

CLKR

FSR

DR

DSP

TMS320C26

The Data Out (Dout) can be connected directly

to the Data Receive (DR) of the DSP and both

elements use the same externally provided clock.

The minimal hold time for DR after falling edge

of CLKR is 20ns where the typical hold time for

the SP8531 is 50ns making the data read valid.

Note that although the SP8531 is essentially a

12 bit converter, it sends 16 bits with the four

MSB’s as zero’s.