MCP79520 datasheet(36/58 Pages) MICROCHIP

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MCP7951X/MCP7952X

DS20002300D-page 36

 2012-2022 Microchip Technology Inc.and its subsidiaries

6.0

ON-BOARD MEMORY

The MCP7952X has 2 Kbits (256 bytes) of EEPROM,

while the MCP7951X has 1 Kbit (128 bytes) of

EEPROM. In addition, the devices have 16 bytes of

protected EEPROM for storing crucial information and

64 bytes of SRAM for general purpose usage. The

SRAM is retained when the primary power supply is

removed if a backup supply is present and enabled.

Since the EEPROM is nonvolatile, it does not require a

supply for data retention.

Although the SRAM is a separate block from the RTCC

registers, they are accessed using the same

instructions, READ and WRITE. The EEPROM is

accessed using the EEREAD and EEWRITE instructions

and the protected EEPROM is accessed using the

IDREAD and IDWRITE instructions. RTCC and SRAM

can be accessed for reads or writes immediately after

starting an EEPROM write cycle.

6.1

SRAM/RTCC Registers

The RTCC registers are located at addresses 0x00 to

0x1F and the SRAM is located at addresses 0x20 to

0x5F. The SRAM can be accessed while the RTCC

registers are being internally updated. The SRAM is not

initialized by a Power-on Reset (POR).

Neither the RTCC registers nor the SRAM can be

accessed when the device is operating off the backup

power supply.

6.1.1

SRAM/RTCC REGISTER WRITE

SEQUENCE

The device is selected by pulling CS low. The 8-bit

WRITE instruction is transmitted to the MCP795XX

followed by an 8-bit address. Next, the data to be

written is transmitted.

There is no limit to the number of bytes that can be

written in a single command. However, because the

RTCC registers and SRAM are separate blocks, writing

past the end of each block will cause the internal

Address Pointer to roll over to the beginning of the

same block. Specifically, the Address Pointer will roll

over from 0x1F to 0x00 and from 0x5F to 0x20.

Each data byte is latched into memory as it is received.

Once all data bytes have been transmitted, CS is

driven high to end the operation (Figure 6-1).

6.1.2

SRAM/RTCC REGISTER READ

SEQUENCE

The device is selected by pulling CS low. The 8-bit

READ instruction is transmitted to the MCP795XX

followed by an 8-bit address.

After the READ instruction and address are sent, the

data stored in the memory at the selected address is

shifted out on the SO pin. Data stored in the memory at

the next address can be read sequentially by

continuing to provide clock pulses to the client. The

internal Address Pointer automatically increments to

the next higher address after each byte of data is

shifted out. The Address Pointer allows the entire

memory block to be serially read during one operation.

The read operation is terminated by driving CS high

(Figure 6-2).

Because the RTCC registers and SRAM are separate

blocks, reading past the end of each block will cause

the Address Pointer to roll over to the beginning of the

same block. Specifically, the Address Pointer will roll

over from 0x1F to 0x00 and from 0x5F to 0x20.

FIGURE 6-1:

SRAM/RTCC WRITE SEQUENCE

910 11

Data Byte 1

SCK

567

33 34 35

38 39

543

Data Byte n

SCK

26 27 28 29 30 31

321

Data Byte 3

321

Data Byte 2

36 37

Instruction

Address Byte

A7 A6 A5 A4 A3

A1 A0

12 13 14 15 16 17 18 19 20 21 22 23

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