34LC02-ISLASHP datasheet(14/40 Pages) MICROCHIP

14 / 40 page

34AA02/34LC02

DS20002029G-page 14

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9.0

READ OPERATION

Read operations are initiated in the same way as write

operations, with the exception that the R/W bit of the

client address is set to ‘

1’. There are three basic types

of read operations: current address read, random read

and sequential read.

9.1

Current Address Read

The 34XX02 contains an Address Pointer that

maintains the address of the last word accessed,

internally incremented by one. Therefore, if the

previous access (either a read or write operation) was

to address ‘

n’, the next current address read operation

would access data from address

n+1.

Upon receipt of the client address with R/W bit set

to ‘

1’, the 34XX02 issues an Acknowledge and

transmits the 8-bit data word. The host will not

acknowledge the transfer, but does generate a Stop

condition and the 34XX02 discontinues transmission

(Figure 9-1).

9.2

Random Read

Random read operations allow the host to access any

memory location in a random manner. To perform this

type of read operation, the word address must first be

set. This is done by sending the word address to the

34XX02 as part of a write operation. Once the word

address is sent, the host generates a Start condition

following the Acknowledge. This terminates the write

operation, but not before the internal Address Pointer is

set. The host then issues the control byte again, but

with the R/W bit set to a ‘

1’. The 34XX02 then issues

an Acknowledge and transmits the 8-bit data word. The

host will not acknowledge the transfer, but does

generate

Stop

condition

and

the

34XX02

discontinues transmission (Figure 9-2).

9.3

Sequential Read

Sequential reads are initiated in the same way as a

random read, with the exception that after the 34XX02

transmits the first data byte, the host issues an

Acknowledge, as opposed to a Stop condition in a

random read. This directs the 34XX02 to transmit the

next sequentially addressed 8-bit word (Figure 9-3).

To provide sequential reads, the 34XX02 contains an

internal Address Pointer, which is incremented by one

at the completion of each operation. This Address

Pointer allows the entire memory contents to be serially

read during one operation.

9.4

Contiguous Addressing Across

Multiple Devices

The Chip Select bits (A2, A1, A0) can be used to

expand the contiguous address space for up to 16K bits

by adding up to eight 34XX02 devices on the same

bus. In this case, the software can use A0 of the control

byte as address bit A8, A1 as address bit A9 and A2 as

address bit A10. It is not possible to sequentially read

across device boundaries.

9.5

Noise Protection and Brown-Out

The 34XX02 employs a VCC threshold detector circuit

which disables the internal erase/write logic if the VCC

is below 1.35V at nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure

proper device operation, even on a noisy bus.

FIGURE 9-1:

CURRENT ADDRESS READ

Bus Activity

Host

SDA Line

Bus Activity

Control

Byte

Data Byte

10 1

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