34LC02T-ESLASHMS datasheet(10/40 Pages) MICROCHIP

10 / 40 page

34AA02/34LC02

DS20002029G-page 10

 2007-2022 Microchip Technology Inc. and its subsidiaries

6.0

WRITE OPERATIONS

6.1

Byte Write

Following the Start signal from the host, the device

code(4 bits), the Chip Select bits (3 bits) and the R/W

bit, which is a logic-low, are placed onto the bus by the

host transmitter. This indicates to the addressed client

receiver that a byte with a word address will follow, once

it has generated an Acknowledge bit during the ninth

clock cycle. Therefore, the next byte transmitted by the

host is the word address and will be written into the

Address Pointer of the 34XX02. After receiving another

Acknowledge signal from the 34XX02, the host device

will transmit the data word to be written into the

addressed memory location. The 34XX02 acknowl-

edges again and the host generates a Stop condition.

This initiates the internal write cycle, which means that

during this time, the 34XX02 will not generate Acknowl-

edge signals (Figure 6-1).

If an attempt is made to write to the array when the

software or hardware write protection has been

enabled, the device will acknowledge the command, but

no data will be written. The write cycle time must be

observed even if the write protection is enabled.

6.2

Page Write

The write control byte, word address and the first data

byte are transmitted to the 34XX02 in the same way as

in a byte write. Instead of generating a Stop condition,

the host transmits up to 15 additional data bytes to the

34XX02, which are temporarily stored in the on-chip

page buffer and will be written into the memory after the

host has transmitted a Stop condition.

Upon receipt of each word, the four lower order

Address Pointer bits, which form the byte counter, are

internally incremented by one. The higher order four

bits of the word address remain constant. If the host

should transmit more than 16 bytes prior to generating

the Stop condition, the Address Pointer will roll over

and the previously received data will be overwritten. As

with the byte write operation, once the Stop condition is

received, an internal write cycle will begin (Figure 6-2).

If an attempt is made to write to the array when the

hardware write protection has been enabled, the

device will acknowledge the command, but no data will

be written. The write cycle time must be observed even

if the write protection is enabled.

FIGURE 6-1:

BYTE WRITE

FIGURE 6-2:

PAGE WRITE

Note:

Page write operations are limited to

writing bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples of the page buffer size

(or ‘page size’) and end at addresses that

are integer multiples of page size – 1. If a

page write command attempts to write

across a physical page boundary, the

result is that the data wrap around to the

beginning of the current page (overwriting

data previously stored there), instead of

being written to the next page, as might be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

Bus Activity

Host

SDA Line

Bus Activity

Control

Byte

Word

Address

Data

Bus Activity

Host

SDA Line

Bus Activity

Control

Byte

Word

Address (n)

Data (n)

Data (n + 15)

Data (n + 1)

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