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DS20005704D-page 1

TP5335

Features

• High Input Impedance and High Gain

• Low Power Drive Requirement

• Ease of Paralleling

• Excellent Thermal Stability

• Integral Source-Drain Diode

• Free from Secondary Breakdown

Applications

• Logic-Level Interfaces (Ideal for TTL and CMOS)

• Solid-State Relays

• Analog Switches

• Power Management

• Telecommunication Switches

General Description

The TP5335 is a low-threshold, Enhancement-mode

(normally-off) transistor that utilizes an advanced

vertical DMOS structure and a well-proven silicon gate

manufacturing process. This combination produces a

device with the power handling capabilities of bipolar

transistors and the high input impedance and positive

temperature coefficient inherent in MOS devices.

Characteristic of all MOS structures, this device is free

from

thermal

runaway

and

thermally

induced

secondary breakdown.

Microchip’s vertical DMOS FETs are ideally suited to a

wide range of switching and amplifying applications

where high breakdown voltage, high input impedance,

low input capacitance, and fast switching speeds are

desired.

Package Type

3-lead SOT-23

(Top view)

See Table 2-1 for pin information.

DRAIN

SOURCE

GATE

P-Channel Enhancement-Mode Vertical DMOS FET