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ADRF5474BCZ 数据表(PDF) 7 Page - Analog Devices |
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ADRF5474BCZ 数据表(HTML) 7 Page - Analog Devices |
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7 / 14 page ![]() Data Sheet ADRF5474 P IN CONFIGURATION AND FUNCTION DESCRIPTIONS analog.com Rev. 0 | 7 of 14 Figure 4. Pad Configuration Table 6. Pad Function Descriptions Pad No. Mnemonic Description 1, 3, 4, 6, 7, 11, 16 GND Ground. Bonding of these ground pads are optional. See the Applications Information section. 2 ATTIN Attenuator Input. No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic. 5 ATTOUT Attenuator Output. No dc blocking capacitor is necessary when the RF line potential is equal to 0 V dc. See Figure 5 for the interface schematic. 8 VSS Negative Supply Input. See Figure 8 for the interface schematic. 9 VDD Positive Supply Input. See Figure 7 for the interface schematic. 10 LE Latch Enable Input. See the Theory of Operation section for more information. See Figure 6 for the interface schematic. 12 D2 Parallel Control Input for 2 dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 6 for the interface schematic. 13 D3 Parallel Control Input for 4 dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 6 for the interface schematic. 14 D4 Parallel Control Input for 8 dB Attenuator Bit.See the Theory of Operation section for more information. See Figure 6 for the interface schematic. 15 D5 Parallel Control Input for 8 dB Attenuator Bit. See the Theory of Operation section for more information. See Figure 6 for the interface schematic. Carrier Bottom The carrier bottom is gold metalized and must be directly attached to the ground plane using conductive epoxy. INTERFACE SCHEMATICS Figure 5. ATTIN and ATTOUT Interface Schematic Figure 6. Digital Input Interface Schematic (LE, D2, D3, D4, and D5) Figure 7. VDD Input Interface Schematic Figure 8. VSS Input Interface Schematic |
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