13

2047 2.3 10/23/00

SMS44

SUMMIT MICROELECTRONICS, Inc.

The high order bits of the address byte remain constant.

Should the master transmit more than 16 bytes, prior to

generating the STOP condition, the address counter will

“roll over” and the previously written data will be overwrit-

Figure 10. Read and Write Operations

ten.

As with the byte-write operation, all inputs are

disabled during the internal write cycle. Refer to Figure 10

for the address, ACKnowledge, and data transfer se-

quence.

Typical Write Operation

(Standard memory device type)

A

C

K

R

/

W

A

C

K

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

C

K

S

T

O

P

S

T

A

R

T

Typical Reading Operation

(Alternate memory device type)

Master

SDA

Slave

1

1

0

S

T

A

R

T

A

C

K

B

A

2

B

A

1

A

8

R

/

W

A

C

K

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

C

K

S

T

O

P

Master

SDA

Slave

0

1

10

A

C

K

R

/

W

A

C

K

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

C

K

S

T

O

P

S

T

A

R

T

Writing Configuration Registers

Master

SDA

Slave

01

10

Master

SDA

Slave

Device Type

Address

Bus

Address

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

A

7

A

6

A

5

A

4

A

3

A

2

A

1

A

0

1

C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

A

C

K

R

/

W

A

C

K

S

T

A

R

T

C

7

C

6

C

5

C

4

C

3

C

2

C

1

C

0

Reading the Configuration Register

01

10

A

C

K

R

/

W

A

C

K

S

T

O

P

S

T

A

R

T

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

01

10

Up to 15

additional bytes

can be written

before issuing

the stop.

The host may continue

clocking out data so long as

it provides an ACK response

after each byte.

B

A

2

B

A

1

A

8

B

A

2

B

A

1

X

B

A

2

B

A

1

X

B

A

2

B

A

1

X

2047 Fig10 2.1