UNISONIC TECHNOLOGIES CO.,LTD

UR5596

MOS IC

www.unisonic.com.tw

1

Copyright © 2005 Unisonic Technologies Co.,LTD

QW-R502-045,A

DDR TERMINATION

REGULATOR

DESCRIPTION

The UTC UR5596 is a linear bus termination regulator and

designed to meet JEDEC SSTL-2(Stub-Series Terminated

Logic) specifications for termination of DDR-SDRAM. It also can

be used in SSTL-3 or HSTL(High-Speed Transceiver Logic)

scheme. The device contains a high-speed OP AMP to provide

excellent response to the load transients, and can deliver 1.5A

continuous current and transient peaks up to 3A in the

application as required for DDR-SDRAM termination.

chipset and DIMMs. Besides, an active low shutdown (SHDN)

pin provides Suspend To RAM (STR) functionality. When SHDN

advantage can be obtained in this mode through lower

quiescent current.

output stage has been designed to maintain excellent load

regulation while preventing shoot through. The UTC UR5596

also incorporates two distinct power rails that separates the

analog circuitry from the power output stage. This allows a split

rail approach to be utilized to decrease internal power

dissipation and permits UTC UR5596 to provide a termination

solution for DDRII SDRAM.

FEATURES

* Source and sink current

* Low output voltage offset

* No external resistors required

* Linear topology

* Suspend To Ram (STR) functionality

* Low external component count

* Thermal shutdown protection

SOP-8

*Pb-free plating product number: UR5596L

ORDERING INFORMATION

Ordering Number

Normal

Lead Free Plating

Package

Packing

UR5596-S08-R

UR5596L-S08-R

SOP-8

Tape Reel

UR5596-S08-T

UR5596L-S08-T

SOP-8

Tube