LPC2102 datasheet(8/32 Pages) PHILIPS

8 / 32 page

LPC2101_02_03_1

Preliminary data sheet

Rev. 01 — 18 January 2006

8 of 32

Philips Semiconductors

LPC2101/2102/2103

Single-chip 16-bit/32-bit microcontrollers

P0.21/SSEL1/

MAT3.0

3 [4]

9 [4]

I/O

P0.21 — General purpose Input/output digital pin (GPIO).

SSEL1 — Slave Select for SPI1. Selects the SPI interface as

a slave.

MAT3.0 — PWM output for Timer 3, channel 0.

P0.22/AD0.0

32 [4]

35 [4]

I/O

P0.22 — General purpose Input/output digital pin (GPIO).

AD0.0 — ADC 0, input 0.

P0.23/AD0.1

33 [1]

36 [1]

I/O

P0.23 — General purpose Input/output digital pin (GPIO).

AD0.1 — ADC 0, input 1.

P0.24/AD0.2

34 [1]

37 [1]

I/O

P0.24 — General purpose Input/output digital pin (GPIO).

AD0.2 — ADC 0, input 2.

P0.25/AD0.6

38 [1]

41 [1]

I/O

P0.25 — General purpose Input/output digital pin (GPIO).

AD0.6 — ADC 0, input 6.

P0.26/AD0.7

39 [1]

n.c.

I/O

P0.26 — General purpose Input/output digital pin (GPIO).

AD0.7 — ADC 0, input 7.

P0.27/TRST/

CAP2.0

8 [4]

13 [4]

I/O

P0.27 — General purpose Input/output digital pin (GPIO).

TRST — Test Reset for JTAG interface.

CAP2.0 — Capture input for Timer 2, channel 0.

P0.28/TMS/

CAP2.1

9 [4]

14 [4]

I/O

P0.28 — General purpose Input/output digital pin (GPIO).

TMS — Test Mode Select for JTAG interface.

CAP2.1 — Capture input for Timer 2, channel 1.

P0.29/TCK/

CAP2.2

10 [4]

15 [4]

I/O

P0.29 — General purpose Input/output digital pin (GPIO).

TCK — Test Clock for JTAG interface.

CAP2.2 — Capture input for Timer 2, channel 2.

P0.30/TDI/

MAT3.3

15 [4]

20 [4]

I/O

P0.30 — General purpose Input/output digital pin (GPIO).

TDI — Test Data In for JTAG interface.

MAT3.3 — PWM output 3 for Timer 3.

P0.31/TDO

16 [4]

21 [4]

P0.31 — General purpose output only digital pin (GPIO).

TDO — Test Data Out for JTAG interface.

RTXC1

20 [5]

24 [5]

Input to the RTC oscillator circuit.

RTXC2

25 [5]

29 [5]

Output from the RTC oscillator circuit.

RTCK

26 [5]

n.c.

I/O

Returned test clock output: Extra signal added to the JTAG

port. Assists debugger synchronization when processor

frequency varies. Bidirectional pin with internal pull-up.

Input to the oscillator circuit and internal clock generator

circuits.

Output from the oscillator ampliﬁer.

DBGSEL

Debug select: When LOW, the part operates normally. When

HIGH, debug mode is entered. Input with internal pull-down.

RST

External reset input: A LOW on this pin resets the device,

causing I/O ports and peripherals to take on their default

states and processor execution to begin at address 0. TTL

with hysteresis, 5 V tolerant.

VSS

7, 19, 43

1, 12, 23

Ground: 0 V reference.

Table 3:

Pin description …continued

Symbol

LQFP48

PLCC44

Type

Description

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