LPC2101_02_03_1

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Preliminary data sheet

Rev. 01 — 18 January 2006

12 of 32

Philips Semiconductors

LPC2101/2102/2103

Single-chip 16-bit/32-bit microcontrollers

6.5 Interrupt controller

The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored

IRQ, and non-vectored IRQ as defined by programmable settings. The programmable

assignment scheme means that priorities of interrupts from the various peripherals can be

dynamically assigned and adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC

combines the requests to produce the FIQ signal to the ARM processor. The fastest

possible FIQ latency is achieved when only one request is classified as FIQ, because then

the FIQ service routine does not need to branch into the interrupt service routine but can

run from the interrupt vector location. If more than one request is assigned to the FIQ

class, the FIQ service routine will read a word from the VIC that identifies which FIQ

source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned

to this category. Any of the interrupt requests can be assigned to any of the 16 vectored

IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce

the IRQ signal to the ARM processor. The IRQ service routine can start by reading a

register from the VIC and jumping there. If any of the vectored IRQs are pending, the VIC

provides the address of the highest-priority requesting IRQs service routine, otherwise it

provides the address of a default routine that is shared by all the non-vectored IRQs. The

default routine can read another VIC register to see what IRQs are active.

6.5.1 Interrupt sources

Each peripheral device has one interrupt line connected to the Vectored Interrupt

Controller, but may have several internal interrupt flags. Individual interrupt flags may also

represent more than one interrupt source.

6.6 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the

pin and the on chip peripherals. Peripherals should be connected to the appropriate pins

prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any

enabled peripheral function that is not mapped to a related pin should be considered

undefined.

The Pin Control Module with its pin select registers defines the functionality of the

microcontroller in a given hardware environment.

After reset all pins of Port 0 are configured as input with the following exceptions: If debug

is enabled, the JTAG pins will assume their JTAG functionality. The pins associated with