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74ACT04SC 数据表(PDF) 2 Page - ON Semiconductor |
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74ACT04SC 数据表(HTML) 2 Page - ON Semiconductor |
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2 / 11 page ![]() 74AC04, 74ACT04 www.onsemi.com 2 ORDERING INFORMATION Order Number Package Number Package Description 74AC04SC M14A 14−Lead Small Outline Integrated Circuit (SOIC), JEDEC MS−012, 0.150” Narrow 74AC04MTC MTC14 14−Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO−153, 4.4 mm Wide 74ACT04SC M14A 14−Lead Small Outline Integrated Circuit (SOIC), JEDEC MS−012, 0.150” Narrow 74ACT04MTC MTC14 14−Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO−153, 4.4 mm Wide NOTES: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. All packages are lead free per JEDEC: J−STD−020B standard. Figure 1. Connection Diagram Figure 2. Logic Symbol IEEE/IEC PIN DESCRIPTION Pin Description An Inputs On Outputs RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC Supply Voltage AC ACT 2.0 4.5 6.0 5.5 V VI Input Voltage 0 VCC V VO Output Voltage 0 VCC V TA Operating Temperature −40 +85 °C DV / Dt Minimum Input Edge Rate, AC Devices: VIN from 30% to 70% of VCC,VCC at 3.3 V, 4.5 V, 5.5 V 125 mV/ns DV / Dt Minimum Input Edge Rate, ACT Devices: VIN from 0.8 V to 2.0 V, VCC at 4.5 V, 5.5 V 125 mV/ns Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. |
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