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1

BURN IN CIRCUIT

*

These components are used to stabilize device due to

poor high frequency characteristics of burn in board.

**

Input signals are calculated to result in internal power

dissipation of approximately 2.1W at case temperature

= 125°C.

SG

PARAMETER

SYMBOL TEMP. POWER

TEST CONDITIONS

MIN

MAX

UNITS

1

Quiescent current

I

Q

25°C

±40V

V

30

mA

1

Input offset voltage

V

OS

25°C

±40V

V

±6

mV

1

Input offset voltage

V

OS

25°C

±10V

V

±12

mV

1

Input offset voltage

V

OS

25°C

±45V

V

±7

mV

1

Input bias current, +IN

+I

B

25°C

±40V

V

±30

nA

1

Input bias current, –IN

–I

B

25°C

±40V

V

±30

nA

1

Input offset current

I

OS

25°C

±40V

V

±30

nA

3

Quiescent current

I

Q

–55°C

±40V

V

75

mA

3

Input offset voltage

V

OS

–55°C

±40V

V

±11.2

mV

3

Input offset voltage

V

OS

–55°C

±10V

V

±17.2

mV

3

Input offset voltage

V

OS

–55°C

±45V

V

±12.2

mV

3

Input bias current, +IN

+I

B

–55°C

±40V

V

±115

nA

3

Input bias current, –IN

–I

B

–55°C

±40V

V

±115

nA

3

Input offset current

I

OS

–55°C

±40V

V

±115

nA

2

Quiescent current

I

Q

125°C

±40V

V

30

mA

2

Input offset voltage

V

OS

125°C

±40V

V

±12.5

mV

2

Input offset voltage

V

OS

125°C

±10V

V

±18.5

mV

2

Input offset voltage

V

OS

125°C

±45V

V

±13.5

mV

2

Input bias current, +IN

+I

B

125°C

±40V

V

±70

nA

2

Input bias current, –IN

–I

B

125°C

±40V

V

±70

nA

2

Input offset current

I

OS

125°C

±40V

V

±70

nA

4

Output voltage, I

V

O

25°C

±18V

R

10

V

4

Output voltage, I

V

O

25°C

±45V

R

40

V

4

Output voltage, I

V

O

25°C

±30V

R

24

V

4

Current limits

I

CL

25°C

±17V

R

.6

.89

A

4

Stability/noise

E

N

25°C

±40V

R

1

mV

4

Slew rate

SR

25°C

±40V

R

2

10

V/µs

4

Open loop gain

A

OL

25°C

±40V

R

96

dB

4

Common mode rejection

CMR

25°C

±15V

R

74

dB

6

Output voltage, I

V

O

–55°C

±18V

R

10

V

6

Output voltage, I

V

O

–55°C

±45V

R

40

V

6

Output voltage, I

V

O

–55°C

±30V

R

24

V

6

Stability/noise

E

N

–55°C

±40V

R

1

mV

6

Slew rate

SR

–55°C

±40V

R

2

10

V/µs

6

Open loop gain

A

OL

–55°C

±40V

R

96

db

6

Common mode rejection

CMR

–55°C

±15V

R

74

dB

5

Output voltage, I

V

O

125°C

±14.3V

R

6.3

V

5

Output voltage, I

V

O

125°C

±45V

R

40

V

5

Output voltage, I

V

O

125°C

±30V

R

24

V

5

Stability/noise

E

N

125°C

±40V

R

1

mV

5

Slew rate

SR

125°C

±40V

R

2

10

V/µs

5

Open loop gain

A

OL

125°C

±40V

R

96

dB

5

Common mode rejection

CMR

125°C

±15V

R

74

dB

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This data sheet has been carefully checked and is believed to be reliable, however, no responsibility is assumed for possible inaccuracies or omissions. All specifications are subject to change without notice.

PA10MU REV L JULY 2002 © 2002 Apex Microtechnology Corp.