A1

A1

D1 (D1N)

D2 (D2N)

D3 (D3N)

D4 (D4N)

D5 (D5N)

D6 (D6N)

D7 (D7N)

D8 (D8N)

A2

A2

A2

Data

Data

Data

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

Valid

Data

FP

Parallel Data•

Output Summary

A1

A1

A1

A2

A2

A2

DATA

SONET STS-3 Framing Sequence

DATA

DATA

DATA

DATA

Resynch

BYCKO

t

D

CLKI

(CLKIN)

OOFN

DI (DIN)

BYCKO (BYCKON)

High speed differential clock input

Frame recovery clock input

High speed serial data inputs

Frame detection confirm output

Byte clock output

(1)

1) Negative edge is active edge.

2) The parallel data outputs only begin showing valid data after the last A2 of the SONET framing sequence. The example

waveforms shown above use an STS-3 framing sequence for convenience, thus valid data is output after the third

A2 in the sequence.

= Don’t care.

NOTES:

(2)