18

Integrated

Circuit

Systems, Inc.

ICS950218

0466B—03/17/04

All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no

defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard

skew described below as Tpci.

Un-Buffered Mode 3V66 & PCI Phase Relationship

3V66

PCICLK_F and PCICLK

Tpci

Group Skews at Common Transition Edges

GROUP

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

3V66

3V66

3V66 (5:0) pin to pin skew

0

250

ps

PCI

PCI

PCI_F (2:0) and

PCI (6:0) pin to pin skew

0

500

ps

3V66 to PCI

3V66 (5:0) leads 33MHz PCI

1.5

3.5

ns