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PCA2117DUGS/DA 数据表(PDF) 33 Page - NXP Semiconductors |
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PCA2117DUGS/DA 数据表(HTML) 33 Page - NXP Semiconductors |
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33 / 107 page  PCA2117 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 8 April 2015 33 of 107 NXP Semiconductors PCA2117 Automotive LCD driver for character displays The chip can be put into power-down mode by applying a HIGH-level to pin PD. In power-down mode, all static currents are switched off (no internal oscillator, no bias level generation and all LCD outputs are internally connected to VSS). During power-down, information in the RAM and the chip state are not preserved. Instruction execution during power-down is not possible. (1) If previously enabled. Remark: When bits D (Table 25 on page 20), CPE (Table 30 on page 24), and TME (Table 32 on page 26) are logic 0, the internal clock signal is switched off. Fig 11. Recommended power-down sequence when using an externally supplied VLCD and the internal clock signal |
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